I'm working with the DECA board, I'm using the Basic Function to generate a PLL with the ALTPLL tool. Everything works fine with lower frequency from 1kHz-1MHz, the problem stars when I'm trying to generate higher frequency like 5MHz to 100MHz, the input clock is the base clock of 50MHz.
For the higher frequency the distortion of the square signal start to figure out as a sinusoidal signal, I attach different reference image from the oscilloscope for the distortion signal at different high frequencies.
I want to know if this is a normal behavior of the DECA board, or I'm messing any additional configuration, I base on documentation "1_FPGA_Intro_Lab" from the DECA board to configure the ALTPLL
Putting my thought anyway.
What compensation mode did you use?
Check if you are driving the PLL output clock to a FPGA pin which is creating some contention on board? Try assigning to other pin.
Check the clock internally using Signal Tap Analyzer.
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