DFE and CTLE reconfiguration in Arria V GZ

[PPerd2]

Hello, FPGA-engineers.

I have a problem with implementation RX equalization in 10GBASE-KR PHY IP in Arria V GZ.  
My project works correctly with Auto-Negotiation (reconfiguration PMA), Link-Training (reconfiguration PCS) and FEC options. 

But when I enable options "Enable RX equalization" in 10GBASE-KR PHY settings and "Enable DFE block", "Enable AEQ block" in Transceiver Reconfiguration Controller settings  -- nothing happens.
I.e., the 10GBASE-KR PHY does not initiate a DFE and CTLE reconfiguration process. Signals dfe_start_rc and ctle_start_rc are always zero. 
I tested in modelsim and in hardware. Why is this happening?

Screenshots of settings 10GBASE-KR PHY:

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Screenshots of settings Transceiver Reconfiguration Controller:

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Screenshots of settings Reset Controller:

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Apart from this I found an old project example and there was a similar problem -- signals dfe_start_rc and ctle_start_rc are always zero.

Part of wave in Modelsim:

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I will be grateful for any help.

[Deshi_Intel · Accepted solution]

HI,

I read from below KDB guideline, Enable the setting in transceiver reconfig controller only "enable the register spacing of the feature, but the feature itself is not enabled by default".

• https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd08142013_117.html

User is still expected to perform dynamic reconfig write/read on the run time to enable the feature.

Thanks.

Regards,

dlim

[Deshi_Intel]

For instance, you can reer to user guide page 579,580 (table 17-15, 17-16) for the register access of controlling AEQ register.

Thanks.

Reagrds,

dlim

[Deshi_Intel]

I forgot to share the user guide line as earlier reply.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/xcvr_user_guide.pdf

[Deshi_Intel]

HI,

I have not hear back from you for quite some time.

Hopefully my earlier feedback is useful to you and you are making progress in your project development

For now, I am setting this case to closure.

Thanks.

Regards,

dlim