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Novice
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DFE and CTLE reconfiguration in Arria V GZ

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Hello, FPGA-engineers.

I have a problem with implementation RX equalization in 10GBASE-KR PHY IP in Arria V GZ.  
My project works correctly with Auto-Negotiation (reconfiguration PMA), Link-Training (reconfiguration PCS) and FEC options. 

But when I enable options "Enable RX equalization" in 10GBASE-KR PHY settings and "Enable DFE block", "Enable AEQ block" in Transceiver Reconfiguration Controller settings  -- nothing happens.
I.e., the 10GBASE-KR PHY does not initiate a DFE and CTLE reconfiguration process. Signals dfe_start_rc and ctle_start_rc are always zero. 
I tested in modelsim and in hardware. Why is this happening?

Screenshots of settings 10GBASE-KR PHY:

 

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ScreenShot234.pngScreenShot235.pngScreenShot236.pngScreenShot237.pngScreenShot238.png

Screenshots of settings Transceiver Reconfiguration Controller:

 

 

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ScreenShot239.png

Screenshots of settings Reset Controller:

 

 

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ScreenShot240.png

Apart from this I found an old project example and there was a similar problem -- signals dfe_start_rc and ctle_start_rc are always zero.

 

Part of wave in Modelsim:

 

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ScreenShot241.png

I will be grateful for any help.

 

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Accepted Solutions
Highlighted
Moderator
125 Views

HI,


I read from below KDB guideline, Enable the setting in transceiver reconfig controller only "enable the register spacing of the feature, but the feature itself is not enabled by default".


User is still expected to perform dynamic reconfig write/read on the run time to enable the feature.


Thanks.


Regards,

dlim



View solution in original post

4 Replies
Highlighted
Moderator
126 Views

HI,


I read from below KDB guideline, Enable the setting in transceiver reconfig controller only "enable the register spacing of the feature, but the feature itself is not enabled by default".


User is still expected to perform dynamic reconfig write/read on the run time to enable the feature.


Thanks.


Regards,

dlim



View solution in original post

Highlighted
Moderator
125 Views

For instance, you can reer to user guide page 579,580 (table 17-15, 17-16) for the register access of controlling AEQ register.


Thanks.


Reagrds,

dlim


Highlighted
Moderator
125 Views
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Highlighted
Moderator
100 Views

HI,


I have not hear back from you for quite some time.


Hopefully my earlier feedback is useful to you and you are making progress in your project development


For now, I am setting this case to closure.


Thanks.


Regards,

dlim


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