Hello,Still rather new to FPGA design, and I had a question about implementing a DMA controller. If a DMA transfer is coordinated from a incrementing memory location to a simple MM-Slave peripheral, like the Altera SPI core, how is flow control properly achieved? I understand that the SPI core can initiate an IRQ event when it's TX Ready bit goes high, but what is the proper way to coordinate the SPI (or other simple CSR peripheral) with the DMA transfer activity? If I am writing a long transfer to a non-incrementing peripheral address, it seems like this would cause TX overflow issues, or the DMA would need to interface with the slave's status registers to coordinate it's next word transfer. Surely the CPU wouldn't be working ISRs for each write if the concept of DMA is to reduce processing overhead? Is it necessary to implement a FIFO on the peripheral slave port? This is a question I've been encountering a lot lately, and I'd like to understand how this kind of transfer coordination takes place. What is the method for equating a TX ready status bit in the target peripheral to a TREADY-like signal for throttling a DMA transaction? Thanks a lot!
You can implement a FIFO yourself (add it as a component and parameterize it) or rely on the Qsys (Platform Designer) interconnect to do this for you. You'll have more control if you add the FIFO yourself.
Thanks for your response. I had no idea that the Platform Designer handled DMA interconnection architecture. Is there some documentation that describes that mechanism? That would have been incredibly helpful earlier on. Are there other automatic functionalities implied that I should be aware of moving forward?Anyway, I'll give this a shot and see how it works out. Thanks again!