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PascalPolygon
Novice
581 Views

DP to MIPI

Hello guys,

Does intel offer an FPGA that supports DP RX and MIPI DSI TX? 

If yes, does the FPGA have a D-PHY bank or is it implementing D-PHY through external resistors?

Lastly, are there any reference designs for that FPGA to bridge DP over to MIPI DSI?

 

Regards,

Pascal.

0 Kudos
11 Replies
Deshi_Intel
Moderator
572 Views

HI,


Unfortunately Intel doesn't has DP to MIPI conversion IP. Both IP is sold as individual standalone IP only.


For DP IP :


For MIPI IP :


Thanks.


Regards,

dlim



PascalPolygon
Novice
568 Views

Hello Deshi,

Thanks for the reply. I see that the MAX 10 FPGA is not included in the supported devices for the DP IP.  Is there anyway to make the DP IP work on the MAX 10 FPGA?

Regards,

Pascal.

Deshi_Intel
Moderator
560 Views

Hi Pascal,


Max10 PLD is targeting low-cost market that doesn't support transceiver channel which is required by Intel DP IP.


This explained why you won't see Intel DP IP offered in Max 10.


You can consider to upgrade to higher grade FPGA like Cyclone V or Arria V for even Cyclone 10 GX for Intel DP IP support.


Thanks.


Regards,

dlim


PascalPolygon
Novice
557 Views

Hello Deshi,

 
Thank you. Here is where my confusion is coming from. On this page (https://www.intel.com/content/www/us/en/products/programmable/fpga/max-10/features.html)  DisplayPort appears as a video interface for the MAX 10 FPGA, but there is an asterisk. What does that mean?
 
Regards,

Pascal.

Deshi_Intel
Moderator
543 Views

Hi Pascal,


Sorry for the confusion.


Byright the * should has a clearer note mentioned something like below

  • IP solution offered may vary on different FPGA product family. Pls check IP solution user guide doc for detail


Regards,

dlim


PascalPolygon
Novice
534 Views

Hello @Deshi_Intel 

Thank you, I think we are going to go with the Cyclone V. Thanks for the helpful information.

Regards,

Pascal.

Deshi_Intel
Moderator
526 Views

Hi Pascal,


You are welcome !


Alright, I am setting this case to closure.


Feel free to file new forum post if you still have enquiry in future.


Thanks.


Regards,

dlim


PascalPolygon
Novice
520 Views

@Deshi_Intel ,

 

Before you close it, one more question. Does the Cyclone V have enough I/O's to drive 2 4-lane DSI channels. That is, I would like to drive 2 mipi displays not just one (8 data lanes, 2 clock lanes).

Regards,

Pascal.

PascalPolygon
Novice
518 Views

@Deshi_Intel 

 

Furthermore, based on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf

 

The difference in resource utilization between SST, and MST(4 streams) is pretty significant. I would like to do MST (2 streams), would that be the same resource utilization as 4 streams or half of it?

 

Regards,

Pascal. 

Deshi_Intel
Moderator
514 Views

Hi Pascal,


Sure, I can answer few more questions for you.


just FYI... Intel support structure is on a case by case basic. That's why we always encourage customer to file new case for new enquiry.


Anyway, now to your questions


  1. I am not familiar with MIPI implementation as I explained to you earlier it's not direct support from Intel. Are you referring to IO pin count or transceiver pin count here ?


Thanks.


Regards,

dlim


PascalPolygon
Novice
497 Views

@Deshi_Intel ,

 

Thanks for the reply, I have more questions about the cyclone V and MIPI. I'll post a new question about those. 

 

Regards,

Pascal. 

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