Does intel offer an FPGA that supports DP RX and MIPI DSI TX?
If yes, does the FPGA have a D-PHY bank or is it implementing D-PHY through external resistors?
Lastly, are there any reference designs for that FPGA to bridge DP over to MIPI DSI?
Unfortunately Intel doesn't has DP to MIPI conversion IP. Both IP is sold as individual standalone IP only.
For DP IP :
- Intel does offer DP IP solution. You can checkout below DP user guide for more info
For MIPI IP :
- Intel doesn't offer MIPI IP solution in house. We are relying on 3rd party design house to offer MIPI IP hence I am not sure about the design implementation detail
- I found out 2 design house that provide MIPI solution. Feel free to engage with them
Max10 PLD is targeting low-cost market that doesn't support transceiver channel which is required by Intel DP IP.
This explained why you won't see Intel DP IP offered in Max 10.
You can consider to upgrade to higher grade FPGA like Cyclone V or Arria V for even Cyclone 10 GX for Intel DP IP support.
Sorry for the confusion.
Byright the * should has a clearer note mentioned something like below
- IP solution offered may vary on different FPGA product family. Pls check IP solution user guide doc for detail
Furthermore, based on this document: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_displayport.pdf
The difference in resource utilization between SST, and MST(4 streams) is pretty significant. I would like to do MST (2 streams), would that be the same resource utilization as 4 streams or half of it?
Sure, I can answer few more questions for you.
just FYI... Intel support structure is on a case by case basic. That's why we always encourage customer to file new case for new enquiry.
Anyway, now to your questions
- I am not familiar with MIPI implementation as I explained to you earlier it's not direct support from Intel. Are you referring to IO pin count or transceiver pin count here ?
- Cyclone V FPGA is offer in many different package with different pin count support. You can checkout more from below Cyclone V ordering code doc
- For the resource utilization on DP MST (2 channel)
- I would say the resource consumption should be between SST and MST (4 channel) but you will need to compile the DP IP in Quartus to checkout the detail