DPRAM synthesised by IP Parameter Editor Pro wont compile

[Oliver_I_Sedlacek]

Moving from Quartus 20.1 Lite to Quartus 23.1 Pro I used the IP editor to generate a fresh DPRAM design, simple enough 128 words of 32 bits with separate read and write ports. Target is Cyclone 10 GX 220 on the eval board.

The problem is that I get 5 identical compiler error in the Analysis and synthesis of:

Error(15465): WYSIWYG primitive "rsproc|rb|ram_2port_0|altera_syncram_component|auto_generated|altsyncram1|ram_block2a23" has clk0 port that must be connected

I instantiate the component in VHDL like this:

rb : component roiRAM
port map (
data => pcwd, -- data.datain
q => lel, -- q.dataout
wraddress => Std_logic_vector(wea), -- wraddress.wraddress
rdaddress => Std_logic_vector(lea), -- rdaddress.rdaddress
wren => pcwe, -- wren.wren
wrclock => clk62pci, -- wrclock.clk
rdclock => clk100sys -- rdclock.clk
);

Help please, please, please

NB the IP file is in the roiRAM.7z file because this forum wont allow IP files. Please think about this, take as long as you like.

[sstrell]

Can you show the rest of the upper level code around this instantiation?  Where are clk62pci and clk100sys coming from?

[Oliver_I_Sedlacek]

This block is buried deep, but I think you've asked the key question. clk100sys comes from a PLL, no issues, but clk62pci comes from the PCIe endpoint wrapper, which is currently commented out! I'll set up a source for clk62pci and report back.

[Oliver_I_Sedlacek · Accepted solution]

So the problem was no clk62pci, which was a bit harder to fix than anticipated. A PLL was the obvious source for the development stage, but it took a while to get two IOPLLs running off the same 50 MHz input on the Cyclone 10 GX evaluation board.

Thanks for asking the right question.