Data Mask Pins for Cyclone III DDR2 Interface

Programmable Devices

CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

Data Mask Pins for Cyclone III DDR2 Interface

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I am currently trying to implement a 32-bit wide DDR2 interface using 2x MT47H128M16RT-25E:C and a EP3C40F484Cx Cyclone III. When it comes to pin assignments for the data mask pins, I am a bit confused. Application note an-445 (http://www.altera.co.jp/literature/an/an445.pdf) p. 9 states that DM pins on the memory device should be connected to DQ pins on the FPGA, while the pin information (http://www.altera.com/literature/dp/cyclone3/ep3c40.pdf) for my device has both DQ and DM pins. Is it really the case that the DM pins on my FPGA should not be used?

Any shared thoughts or experiences on this would be highly appreciated!

Thomas

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