Dear sir or Madame After comparing Intel’s datasheet and the available down loadable footprint (in this case Mouser) it seems that the footprint mismatches the datasheet.

[SThor8]

According to the footprint data sheet for the 10M02DCV36I7G WLCSP-36 package, pin A1 is up to the left looking from the bottom view.

But if you download the footprint from Mouser it shows

the A1 up to the left, it seems that the creator of the footprint has misunderstood

the datasheet?

Is it a correct interpretation, based on Intel’s

datasheet, that A1 should be up in the left corner if you would make the footprint from scratch (looking from above) ?

The footprints can be found here

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-index/lit-pkg/package.html?family=MAX_10

and more specific

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/packaging/04r00486-00.pdf

[NurAiman_M_Intel]

Hi,

Thank you for contacting Intel community.

I believe the link that was shared was referring to device packaging specification and dimension.

Sorry to let you know that Intel FPGA do not provide support for PCB footprint symbols for FPGA and CPLD device families, similar to configuration devices.

However, we will continue the support by providing the schematic symbol which you can download from the link above. You could have the schematic symbol in .olb format from the link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html

Regards,

Aiman