Default GPIO status of Cyclone 10 LP

[gowtham_m_p]

Hi,

We are using 10CL040YF484C8G in our design. Can you Tell us the default IO status before and after configuration?

As mentioned in Cyclone 10 LP Handbook, 
 
In Section 9.2.2 it is mentioned that before configuration the IO Pins are tri-stated,

but in section 6.3.2 the IO states are mentioned that configured as weak pull-up. 

Please clarify the default status of IO pins in cyclone10 LP FPGA.

Thanks and Regards,

Gowtham M P

[AqidAyman_Intel]

Hi Gowtham M P,

Thank you for reaching out Intel FPGA Community.

I would say, from my understanding, the default I/O status before configuration and after power up is tied to internal weak pull up. The I/O pins will be in tristate condition during the power up is happening.

Regards,

Aqid

[AqidAyman_Intel]

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