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Valued Contributor III

Design constraints for DDR SDRAM interfacing with cyclone3 FPGA

Hi all, 

I need to interface DDR SDRAM Interface with cyclone iii FPGA.In that i 

have used first 2 banks of fpga for ddr interface. 


I also make Vref pin as 1.25v. 


Totally i use vref0,vref1,...vref4 pin as 1.25v all those pins i am using. 


My question is can i connect all 16 data pins in same vref0 or i have to use only 8 data pins in vref0 and remaining in vref1/2/3 like that? 


please clarify me. 🙂
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Valued Contributor III

Re: Design constraints for DDR SDRAM interfacing with cyclone3 FPGA

I face this problem before. You have to do some setting because there is too much bidir pins for 1 Vref.:) 


1st : 

Assigment-Device-Device and Pins option-Dual purpose pins(set all value to: use as regular I/O accept for DClock&nCEO. 

2nd : 

Assigment-Assigment Editor- Change all DQ,DQS and DM pins to (Output Enable Group). For the Value column, set any number same for those pins. 

eg: DQ[0]->Output Enable Group->123456(Value) 

3rd : 

Assigment-Pins(Change IO standard for all DDR related pins to SSTL-2 Class I.) 


You now are able to compile without any fail hopefully. I face this before and want to help you.:o 


Thank you: 

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