Designing lookup table in FPGA

[Altera_Forum]

I am quite new to fpga. I need to build lookup tables in FPGA and a program in C updates the content of these LUT every cycle (roughly 1ms). Could anybody give me some idea how to design it? 

 Thank you for your help.  Fransisco

[Altera_Forum]

Hello, 

 you can achieve this with FPGA internal dual-port RAM. One port is used for updating the table, the other for normal operation. Documentation can be found e. g. from the Quartus Megawizard where the RAM is instantiated.  Regards, Frank

[Altera_Forum]

Thank you Frank for your reply. 

 yes I can instantiate 2 port ram in Quartus megawizard thing but my main concern is how to make the software module (Program in C) update the lookup table created my megawizard (or verilog). My problem is how to make the software (C program in PC) and hardware part (fpga) communicate with each other so that the LUT can be updated after certain interval (1ms).  Thank you very much for your help.

[Altera_Forum]

Hello, 

 I expected a similar problem, too, but you gave no clues how your design may look like. Basically you need to provide some kind of interface at your FPGA that makes it behave as a peripheral to the processor. This could be a parallel data bus of suitable width (8, 16, 32 bit) with control lines and a multiplexed or non-multiplexed address bus, or could be a serial bus as SPI or I2C.   Most important parameters are required throughput and processor abilities. As dual-port RAM operates synchronous (as user defined FPGA logic in most cases, too), it could be meaningful to use a clock from processor in the interface partition. Other option is to use the same clock as in the remaining design and synchronize bus signal processing to this clock.  Regards, Frank

[Altera_Forum]

--- Quote Start ---  My problem is how to make the software (C program in PC) and hardware part (fpga) communicate with each other so that the LUT can be updated after certain interval (1ms).  --- Quote End ---    Every 1ms? Unless you have custom hardware at the PC side, it doesn't sound like an easy task, latency will kill you.  If you can pipeline the transfer, i.e., send one packet at an average rate of 1ms, without waiting for a reply from the FPGA side, then that is feasible. Again, the problem is not the FPGA, but the PC. PC hardware is designed for high bandwidth but slow latency. If the bandwidth required is very small, then you might use the PC parallel (or even serial) port. These ports have no significant latency, but of course, their bandwidth is limited.  "Normal" PC operating systems are not real-time, so there is a system software issue as well. You might need a real-time OS, and not standard Windows/Linux. Plain old DOS might be good enough.  First check your requirements and the PC side, then the FPGA side is (relatively) easy.

[Altera_Forum]

Hello, 

 apparently I overlooked the pc host presented in the last post and thought of an embedded processor. Selecting an appropriate interface and realtime behaviour could be an issue with a PC. Without knowing the required througput, in this case size of the table to be reloaded every ms, this can't be decided, but some extra buffering at the FPGA could be necessary. In any case, a fast standard interface (Ethernet, USB) would be my first choice, although some additional hardware is required.  Regards, Frank