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Altera_Forum
Honored Contributor I
1,799 Views

Detect high impedance on the input pin

Hi to all, 

 

for my little project, I need to manage the output pin of any FPGA placing them at high impedance. This is not a problem, I can do it with MAX10 and Cyclone IV. 

 

However I would need to detect if an input pin is a logic level 0, 1 or disconnected (High-Z).  

 

It is possible?
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6 Replies
Altera_Forum
Honored Contributor I
390 Views

An unconnected High Z Pin gives you only true or false to the internal logic. In order to get the High Z State you need some additional circuitry. 

Some ideas: 

  • connect you pin to VCCIO/2 with a 10k resistor and use a window comparator to detect this level. Maybe this is possible with differential LVDS inputs. 

  • use a external window comparator with 2 digital outputs to the FPGA 

  • connect your pin to another toggling pin with a 10k resistor and try to detect this frequency or pattern (eg: 1MHz) 

  • use a RC combination from your external signal to the FPGA bidir PIN and use short test pulses (with output enable) to charge/discharge the capacitor. The time constant is different depending on the external Level (0, Z, 1) 

  • use a RC combination from your external signal to the FPGA bidir PIN and use short test pulses (with output enable) to discharge the capacitor and a weak pullup to charge 

    measure the time the pin needs to go high: 

    short time: Pin is connected to "1" 

    longer time: Pin is connected to "Z" 

    never: Pin is connected to "0" 

     

Altera_Forum
Honored Contributor I
390 Views

Another idea is to use an "oscillating" bus hold. Use the inverted latched input value as driver for a resistor to the input as programmable pullup/pulldown. In case the external Pin is tristate you have implemented a toggle flipflop with f/2 this way. 

In case the external Pin is push/pull you get "1" or "0". The disadvantage is that you need two Pins for this ...
Altera_Forum
Honored Contributor I
390 Views

Hi DUESTERBERG, thanks for your aswers! 

 

 

--- Quote Start ---  

 

  • connect your pin to another toggling pin with a 10k resistor and try to detect this frequency or pattern (eg: 1MHz) 

 

 

--- Quote End ---  

 

 

This could be ideal solution in my case. 

I have two questions on this solution: 

 

1) How detect the pattern from input pin in VHDL? 

2) Can I use an external oscillator or should I use a FPGA internal pin?
Altera_Forum
Honored Contributor I
390 Views

1) create a pattern on the driving Pin (clock, prbs, ...) and compare the input with the driving signal. If both are the same over some time the Pin is High Z. 

2) you are more flexible with a FPGA Pin, and you know what you are driving (expected data), this depends on what you have available on you board.
Altera_Forum
Honored Contributor I
390 Views

Usually, for busses that are biderectional, there is a master somewhere that knows what direction the bus is driving at all times. For your inputs, there would be a write_enable signal or similar so you know whether the input pins should be Z or not. 

 

Using some external circuitry like those described above seems rather over complicated.
Altera_Forum
Honored Contributor I
390 Views

You are absolutely right, but i don't know the application. Maybe it is something like a hardware in the loop test, not just a "normal" bus ...

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