Developing my own board: Where do I begin?

[Altera_Forum]

I've developed a system on my Nios II Cyclone II dev kit and now I'm interested in creating an actual product. I've decided I want to upgrade to a Cyclone III ep3c25f324i7 with a parallel flash loader and DDR2 memory, but... 

 I'm not sure where to begin. Do I design a system in Quartus first? Does it decide the pin assignments for my FPGA? Or do I choose those myself on my PCB? What things should I keep in what IO banks? What chips am I going to need to be able to program my design? And god help me, there's hundreds of resistors and caps on this board, how many of these do I really need?  If anyone could refer me to a how-to guide for building your own board, it'd be extremely helpful. Thanks!

[Altera_Forum]

Hi Collinsrs: 

 It's a age old question with FPGA's. In realilty, I think you need to kind of work both together.   Here's what I usually do when starting a new project:  First go to http://www.altera.com/literature/lit-dp.jsp and grab all Cyclone III pinout files for the devices in the F324 package. (Usually there are three devices per package that if you're careful, you can scale up/down in with the same board. But you half to be careful, because there are lots of gotcha's. (mainly with VCCINT/GND pins and missing IO's on smaller devices.)  If there are any dev-boards, that are close to your design, grab the schematics for those as well. This is probably the best starting place if you can find something that's close.  Assign a rough pin-out based on area location, bank IO voltage, etc. Keep to using only IO's that are common in all devices in the same package.  Generate a Quartus blank project assigning the desired IO types/voltages, and locations. (I usually generate this from a script that I apply to the xcell pin-out file, so that I don't have to type them again.) (IE I use the Altera Pin-out excell sheet and add another field, then I spit out the set_location_assignments at the end).  I just wish Altera would proved a "Device Package Compatibility Pinout file" It would save me a lot of cross checking between the 3 files.  Once you have that, Hook up dummy logic, so all the io's don't get optimized out, then compile with the migration devices set, and that will tell you if you have any problems you need to fix.  No you have a pinout, you can use for you board, and if you hook up all proper power/grounds for all common devices, you can switch between the larger/smaller devices for the same package.  Pete

[Altera_Forum]

You'll notice, that the parallel flash (I guess, you intend to use Active Parallel configuration scheme) and DDR2 interface constrain your design to some degree. E.g. IO placement restrictions come into play with the DDR2 voltage referenced standards, AP has a lot of fixed pins. 

 Thus it's important, that you check acceptance of your pin placement with a reference design ported to your hardware. Existing evaluations boards are not necessarily a good reference, they sometimes have built-in IO placement conflicts.

[Altera_Forum]

It's really an iterative process. You'll need to move back and forth between the your schematic / PCB / and Quartus continually through the process.  

Here is a rough overview of what I usually do. 1 - Start with determing which IO banks you're going to place specific interfaces on. 2 - I then move to the schematic. Doing the schematic helps you to get a better picture of what the signals are that you'll need. It's helpful to create your FPGA schematic symbol such that the pin names are descriptive enough that you know what they can/should be used for. 3 - Once you've roughly assigned your pins in the schematic, Move into Quartus. Now you can start tweaking your pin assignments and changing the schematic to fit the design requirements. 4 - It's a good idea to envision the physical locations of things on the PCB as you do this. Once you start the actual PCB, you may end up moving A LOT of things around to accommodate the layout. No problem, just change it on the schematic and check with Quartus and the literature to make sure it's a legal assignement. 5 - Whatever schematic/layout tool you use, find the easiest way you can to generate a listing of which signals are connected to which pins on the FPGA. Then use this list to create your pin assignments TCL script for Quartus.  Good Luck,  Jake

[Altera_Forum]

Hi Collinrs 

 What I did was buy one of the CycloneIII EP3C25 kits that cost $199 and used that to start doing the hardware that the Cyclone part interfaced with. Then came the good part, you get the schematic in OrCAD format with the board. I think it is also on the Altera web site if you want to look around. I took their schematic as the start point and stripped away what I didn't need and added what I did. The board worked the first shot with just 2 very minor tweaks. Starting with a working schematic is the best thing in the world.  Al

[Altera_Forum]

And you should note that the parallel flash interface is not available on all parts in the Cyclone family. 

 It is a result of the number of pins on castain packages.  Read the Configuration and Cyclone III Users Handbook carefully.