Difference between true and emulated KVDS RX channels in MAX10 FPGA?

[EHait]

I am designing a board with MAX-10 FPGA. I can't find anywhere reliable comparison between true-LVDS and emulated-LVDS receive channels. 

Are there differences between them in max bitrate? In margin?

What is the maximum achievable bitrate for LVDS RX in DDR mode for true and emulated LVDS inputs for -7 and -8-speed grades 10M50DCF256 devices?

[SreekumarR_G_Intel]

Hello Eli , Thanks for the question , Ture LVDS buffer means it support true differential buffer (i.e if you the transmitter output to receiver should be differential ) Emulated LVDS buffer means two single ended pins to emulate the differential buffer . In the below link , refer figure 8 and 9 for the pictorial example. https://www.intel.com/content/www/us/en/programmable/documentation/sam1394433606063.html No other difference i could think of .. Please refer detail max datarate in below link for speed grade -7 and -8 speed grades https://www.intel.com/content/www/us/en/programmable/documentation/mcn1397700832153.html#mcn1398043804031 Thank you , Regards, Sree

[SreekumarR_G_Intel]

Hello Eli , Can you let me know any further question on this topic , if not can you please close the case ? Thank you , Regards, Sree

[EHait]

Yes, tnanx