Disable scrambler for 10GBASE-R on Cyclone 10 GX?

[PrivateIsland]

Hello,

I'm not able to find a valid configuration for disabling the TX scrambler using the Cyclone 10 GX when configuring the transceiver for 10GBASE-R.   Note that this is for testing, and the RX path can either be disabled or enabled (don't care). 

As the attached figure shows, the Transceiver PHY User Guide conveys that the TX scrambler can be disabled by configuring a mux; however, I am not able to determine how to do this. 

I have tried various options using both the 10GBASE-R and Basic (Enhanced PCS) configuration rules, but the Parameter Editor always indicates errors without providing a valid path to leaving the scrambler disabled.  

Please let me know if there is a valid method to disable the TX scrambler but still have 64B/66B encoding work at the correct line rate of 10.3125-Gbps data rate.  

Perhaps there is a way to do this under the hood (without the Parameter Editor) by modifying the Verilog IP directly?   I haven't tried this yet. 

Thank you. 

[Kshitij_Intel]

Hi,

For the resolution, please refer Table 20 in the link below.

2.4.4. Enhanced PCS Parameters (intel.com)

Thank you,

Kshitij Goel

[CBlow]

Hello,

I generated the 10BASE-R example design and turned off the scrambler.  Platform Designer gives this error with no apparent way to correct.  Is this a bug or are there multiple options that must be selected to turn off the scrambler?

Error: altera_eth_10gbaser_phy.xcvr_native_a10_0: The current value "disabled" (0) for parameter "Enable TX scrambler (10GBASE-R/Interlaken)" (enh_tx_scram_enable) is invalid. Possible valid values are: "enabled" (1). The parameter value is invalid under these current parameter settings: "device_family" (device_family)="" (Cyclone 10 GX) && "Enhanced PCS / PMA interface width" (enh_pcs_pma_width)="32" && "FPGA fabric / Enhanced PCS interface width" (enh_pld_pcs_width)="66" && "Transceiver configuration rules" (protocol_mode)="10GBASE-R" (teng_baser_mode). Rule(s): hssi_10g_tx_pcs_scrm_bypass.

thanks,

Carl

[Kshitij_Intel]

Hi Carl,

Can you please share your project. I will look into it.

Please mention which Quartus version you are using.

Thank you,

Kshitij Goel

[PrivateIsland]

Hello,

I should be able to submit a test project this week that shows this problem.   It will be using Quartus Pro 23.4 for Cyclone 10 GX.

Thank you

[CBlow]

Hello,

Here's the example project created in Platform Designer, v22.4

[Kshitij_Intel]

Hi,

I have compiled your shared project, it doesn't give me any compilation error.

Thank you,

Kshitij Goel

[CBlow]

Hello,

To duplicate the error, Please go into the 10GBASER_PHY IP settings and under the Enhanced PCS page please uncheck Enable TX scrambler.

Thanks,

Carl

[Kshitij_Intel]

Hi,

If you are choosing Transceiver Configuration Rule to 10G Base-R or Interlaken. You cannot just disable scrambler with your current configuration. Also, if you choose Basic (Enhanced PCS) you can disable the scrambler, but you also need to disable the 64b/66b encoder.

Thank you,

Kshitij Goel

[Kshitij_Intel]

Hi,

As we do not receive any response from you on the previous reply that we have provided. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you,

Kshitij Goel

[PrivateIsland]

Thank you K**bleep**ij . It's OK to close this out, but I am hoping that Intel/Altera will update its documentation to reflect the limitations of the transceiver. 

The current documentation conveys a simple mux  after the scrambler that would enable a bypass of it.   I believe the documentation and previously attached figure should be changed to point out the limitations detailed in this forum thread.