Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20403 Discussions

Do I have to have masters and slaves in a large shift register?


I'm trying to build a shift register of 2^24 (= 16,777,216) bits. The shift register has two input bits, (dataIn) and (shift), and one output bit, (dataOut). Bit (dataOut) is always the value of bit 16,777,215. If (shift) is zero, then all 16,777,216 bits retain their current value. If (shift) is one, then the value of each bit i from 0 to 16,777,214 gets written to bit (i + 1), and the value of (dataIn) gets written to bit 0.


Can I do this with one bit of storage for each of the 16,777,216 bits, or does my storage have to have a slave bit and a master bit for each of the 16,777,216 bits?


What concerns me is the potential, without a master / slave architecture, for bit j to overwrite bit (j + 1) before the value of (j + 1) can write itself to (j + 2), resulting in the loss of the value of bit (j + 1). Is there a way to time the assertion of (shift) so that this doesn't happen? Or do I have to have masters and slaves to keep this from happening?


0 Kudos
2 Replies
New Contributor III

I hope you've tried this by now... that's quite a shift register...


I trust you've discovered that you only need 1 FF per bit - providing you're clocking the entire shift register synchronously. There's no need for any 'master/slave architecture'.




0 Kudos
Valued Contributor III

Heh what device do you think you will be able to implement a register-based 16M bit shift register in? And have any room left to do anything else?


For any real implementation a ram-based architecture based on an Altera ALTSHIFT_TAPS megafunction would be a much better solution.

0 Kudos