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Altera_Forum
Honored Contributor I
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Do you have any idea how to flush the FIFO?

I'm transferring data from FPGA to HPS using h2f-sdram bridge which is connected to sgdma. 

My system includes multiple FIFOs ( Avalon FIFO memory and write master FIFO) 

 

I want to be able to clear my FIFO (Avalon FIFO memory) whenever I start a new transfer in my design. 

 

Is there a simple way to do that? 

 

I also want to flush the write master FIFO - would you please suggest a way to do that? 

 

Thank you :cool:
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