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Altera_Forum
Honored Contributor I
1,040 Views

Documentation discrepency for MAX10m50 pin outs

Hi All, 

I am designing a board with a MAX10m50SCE144. I downloaded the Excel pinout spreadsheet which shows CLK0n and CLK0p on pins 25 & 26 and CLK1n and CLK1p are on 27 & 28. But in the Quartus Pin Planner (for the same part) the clock pins are shown on pins 26 & 27 for CLK0 and on pins 28 & 29 for CLK1. Which document is correct?? 

 

Both of these documents are the very latest versions which I downloaded over the last few days so I don't believe I'm looking at aged documents. 

 

 

Thanks, 

Scott
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2 Replies
Altera_Forum
Honored Contributor I
47 Views

Hi Scott, 

 

Can you provide the screenshot of pin conflicts? 

we have checked the document but not able to get the conflict.The Quartus pin planner for device MAX10m50SCE144 with Device Excel pinout spreadsheet is same. 

 

find the attachment for screenshot. 

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance. 

 

Best Regards 

Vikas Jathar  

Intel Customer Support – Engineering 

(Under Contract to Intel)
Altera_Forum
Honored Contributor I
47 Views

Hi Vikas, 

 

I worked on the project yesterday and noticed that the pin planner display has changed. It now matches the Excel spreadsheet. I don't know what has happened, but the two sources are now in agreement. Several times before yesterday, the clock pins in bank 1B (of the MAX10m50SCE144 were shifted down by one pin so the first falling clock signal was located on pin 26. I wish I'd taken a screen capture, but hadn't. 

 

Thanks, 

Scott
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