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xytech
New Contributor I
453 Views

Does A10 GX device's banks need individual clocks input from the dedicated CLK pins for DDR4 ?

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Hi, there,

we use A10 GX(10AX057H3F34E2SG) for one DDR4 SO-DIMM mempry card. bit width 64, and three FPGA banks are used.

In our previous experience for DDR3, these banks do not necessarily need their own input clocks from dedicated clock pins. We can use global clocks to generate clocks for driving DDR IP.

 

However, I read on Altera Dev Kit reference schematic, it indeed provides an independant clock input on dedicated pins of DDR-Banks.

 

Please look at the attached pdf sch. On page8, the Bank 2K(connects with memory connector J14 on page17), dedicated clk pins F34/F35 are provided with CLK_EMI_P/N that comes from clock IC (U26 Si5338A-CUSTOM). Also, not sure what is the frequency of U26 ouput as it's custom.

 

So, Why bother to do so, with more cost on additional custom clock ICs? Cann't they just use global clocks? Any special considerations?

 

Hope some Intel expert could kindly help on this. Thanks. Happy weekend.

 

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1 Solution
NurAida_A_Intel
Employee
49 Views

Hi xytech,

Thank you so much for the details clarification. It really helps to understand the issue better.

Yes, your understanding is correct. Since the current clock source is not a dedicated to the PLL that you want to use with your DDR4, then you need to add another clock device to feed the ref_clk.  Please note that using additional clock will slightly give effect to the clock jitter and timing margin which also mentioned in the handbook.

Thanks

Regards,

NAli1

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8 Replies
xytech
New Contributor I
49 Views

UP

xytech
New Contributor I
49 Views

@NathanR_Intel​  Hi Nathan, if you have time, may you pls help to take a look on this? thanks!

xytech
New Contributor I
49 Views

up​

NurAida_A_Intel
Employee
49 Views

Hi xytech,

 

You must use external dedicated clock inputs for the PLL ref clock driving the clock tree.

External memory interfaces that span multiple banks use the PLL in each bank. The relatively short span of the PHY clock trees results in low jitter and low duty-cycle distortion, maximizing the data valid window.

If you open the DDR4 IP in the IP Parameter Editor, under the "General" tab the recommended PLL ref clock jitter is 10ps. This may change depending on what Memory clock frequency and PLL ref clock frequency you choose, but 10ps (or less) is the generally recommended value.

For more detail, you can refer to "Chapter 2.1.8  PLL Reference Clock Networks" (page 22) of this EMIF handbook --> https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-20115.pdf

 

Hope this helps.

 

Thanks

 

Regards,

NAli1

xytech
New Contributor I
49 Views

Hi, NAli1, thanks for answer. let me be more specific. Now we only have one differantial Main_CLK connect to FPGA from Bank 2J's dedicated PLL input pins (AP24, AN24), the clock jitter before FPGA is 180fs. However, DDR4 uses 3 banks : 3D, 3E, 3F, with all command and adress pins located in bank 3E.

Quote UG-20115 page 225-226 section 6.3.2.2 "For the clock source, use the clock input pin specifically dedicated to the PLL that you want to use with your external memory interface. The input and output pins are only fully compensated when you use the dedicated PLL clock input pin. If the clock source for the PLL is not a dedicated clock input pin for the dedicated PLL, you would need an additional clock network to connect the clock source to the PLL block. Using additional clock network may increase clock jitter and degrade the timing margin", and section 2.1.8 "If you plan to use an on-board oscillator, you must ensure that its frequency matches the PLL reference clock frequency that you select from the displayed list" .

So, from your infoamtion, We should add another clock device such as clock IC or Oscillators or Crystals on board and connect its outputs into decicated PLL inputs pins of either one of Bank 3D/3E/3F.If I use Bank 3E, the pins should be G5/G6 or F5/F6. Also, the jitter and frequency should be properly selected . And we CAN NOT use the exsisting MAIN_CLK + Global clock NETWORK to feed ref_clk input of DDR4 controller as pic below (figure 11 of UG-20115). Is my understanding correct?

Thank you very much!

ddr.png

 

 

NurAida_A_Intel
Employee
50 Views

Hi xytech,

Thank you so much for the details clarification. It really helps to understand the issue better.

Yes, your understanding is correct. Since the current clock source is not a dedicated to the PLL that you want to use with your DDR4, then you need to add another clock device to feed the ref_clk.  Please note that using additional clock will slightly give effect to the clock jitter and timing margin which also mentioned in the handbook.

Thanks

Regards,

NAli1

View solution in original post

xytech
New Contributor I
49 Views

Thanks, NAli1.

 

By the way, may I ask how do Intel employee responds to different questions in different sections of forum? For example, someone posted two questions on two seperate thread about A10 GX device and Cyclone 10 LP device, will there be specific Intel personel to deal with them respectively according to devices families, or just handle these questions randomly if any intel gyus read the new threads? Thanks.

NurAida_A_Intel
Employee
49 Views

​Hi xytech,

 

This platform is open for community.  Anyone who have the answer/solution to the issue are welcome to answer the thread 😊

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