In the ug of CVP,
6. Understanding the Design Steps for CvP Initialization
and Update Mode in Intel Stratix 10
6.1. Implementation of CvP Initialization Mode
CvP Initialization mode splits the bitstream into periphery and core images. The
periphery image is stored in a local flash device on the PCB. The core image is stored
in host memory. You must download the core image to the FPGA using the PCI
You must specify CvP Initialization mode in the Intel Quartus Prime Pro Edition
software by selecting the CvP Settings Initialization and Update and you must also
instantiate the Avalon-ST Intel Stratix 10 Hard IP for PCI Express(4).
(4) CvP also supports Avalon-MM.
it suppose that CvP supports AVALON-MM , I hope someone could verity it. Thanks.
I think there is some mis-understanding on the user guide. The CvP also support Avalon-MM is refering to the Avalon-MM PCIe IP as if you look into the user guide, it mention that you need to use "Avalon-ST Intel Stratix 10 Hard IP for PCI Express" IP with note 4 where you can also use the Avalon-MM version of IP in order to implement your Quartus design with CvP features.