We have an IoT application that utilizes the MAX V CPLD. Due to nuances in the design, non-negligible power savings will occur if we are able to step down from the standard 3.3V to a non-standard 2.8V I/O voltage. Does the MAX V support this? If so, should we set the I/O standard to 2.5V or 3.3V in Quartus?
Many thanks for your help
Since the MaxV CPLD only supports 1.5V/1.8V/2.5V/3.3V , you may have to set the Bank Vccio voltages to 2.5 and use an external resistor to drop the voltage down to 2.5 volts at the inputs. The FPGA pins/banks will may not be able to tolerate 2.8V when set to 2.5V.
As for using 3.3V Vccio, when you drive 2.8V signal into the IO pins, there's a possibility that logic 1 may not get read correctly ( difference of .5V).
By setting the VCCIO 3.3V you can achieve minimum and maximum range of 3.0V to 3.6V. For VCCIO 2.5V you can achieve minimum and maximum range of 2.375V to 2.625V.
Refer link below to Table 3-6 Page 54 & Table 3-7 Page 55 for the minimum and maximum I/O Supply Voltage.