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JChoi2
Beginner
283 Views

Does tx_outclock of ALTLVDS_TX have to be connected to dedicated clock output pin?

I use Stratix V/ Arria10 Device.

I made serdes with ALTLVDS_TX.

I want output tx_outclock of ​ALTLVDS_TX to pin.

Does tx_outclock of ALTLVDS_TX have to be connected to dedicated clock output pin?

Is a regular I/O ok?

In ALTLVDS_TX case, dedicated clock pin has better Jitter than regular i/o?

 

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4 Replies
HBhat2
New Contributor II
43 Views

Hi,

 

As tx_outclock generated from a PLL, it is better to assign to a dedicated clock output pin for better jitter performance and clock specific routing inside the FPGA.

 

With Regards,

HPB

JChoi2
Beginner
43 Views

​Thank you HPB

 

>As tx_outclock generated from a PLL,

 

In my case, the outclock divide factor is 2,

then tx_outclock is generated from serdes, the tx_in of serdes is "10101010.."

tx_outclock is one of the serialized data output port of channel.

 

In this case also, dedicated clock output has  better jitter than regular I/o?

 

Regards

JC 

HBhat2
New Contributor II
43 Views

Hi,

 

TX_outcock is generated by internal PLL itself by taking inclock as the input. The PLL itself divides the reference clock to required frequency and outputs at tx_outclock port. So, in my view, it is better to connect to "PLL_xx_CLKOUT" pin of same bank where tx_out is placed.

 

With regards,

HPB

 

Rahul_S_Intel1
Employee
43 Views

Hi ,

I would recommend you to use dedicated clock pins for jitter performance. The jitter level is low for the dedicated clock pins comparing to regular IO.

 

And I also recommend you to do the compilation on Quartus to make sure that the pins are compact with IO assignments

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