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Hi -
zip file downloaded
Below web :
14. Dynamic Reconfiguration
- (23/06/2016) Arria10 GX SI Board (ES3): 4 Ch Dynamic Reconfiguration Demo Design Using Data rate reconfiguration and TX PLL clock switching. (incl. TTK functionality)
Unpack the Zip file,
All Upgreate is success,
But Compile Error...
Error: Error opening
D:/arria10-siboard-4ch-txpll-and-datarate-reconfiguration/Arria10_SIBoard_4Ch_TXPLL
_and_data_rate_reconfiguration_restored/core_prbs/rate_matcher.qsys.
Thanks
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Hi,
Can you try replacing all the hyphens (-) with underscores (_) in the file path?
Replace 'arria10-siboard-4ch-txpll-and-datarate-reconfiguration' with 'arria10_siboard_4ch_txpll_and_datarate_reconfiguration' or some other name without special characters.
Please try and let me know.
Regards
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Hi- Ash_R
I have tried it
I changed the directory name to 'arria10_siboard_4ch_txpll_and_datarate_reconfiguration'.
But the results are the same.!
Compile Error!
Error: Error opening D:/arria10_siboard_4ch_txpll_and_datarate_reconfiguration/Arria10_SIBoard_4Ch_TXPLL_and_data_rate_reconfiguration_restored/core_prbs/rate_matcher.qsys.
Thank!
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Hi,
I am able to reproduce the issue that you face. Will get back to you with a solution for this. Meanwhile, is it possible for you to choose some other example available on FPGA wiki page?
Regards
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Hi,
I have received the following reply for the issue that you face.
You can just remove that reference in the .qsf to that file as this is not being used in the design.
Also there is an upgraded design for Quartus version 20.4. Attaching here for reference. Please try it out.
Regards
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We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Regards
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