E-tile and F-tile 64b/67b encoding

[mikefr]

Hi,

I want to do SFPDP gen3 with Agilex 7 so I need 64b/67b encoding.

In 683458 "Agilex™ 7 FPGAs and SoCs Device Overview" it is written that PCS of e-tile supports 64b/67b encoding.

I looked in 683723 "E-Tile Transceiver PHY User Guide" but I could not find any information how to configure the IP to use this encoding so how to do this?

For F-tile in "Agilex™ 7 FPGAs and SoCs Device Overview" there is nothing about supported encoding but I found the "F-Tile Interlaken Intel® FPGA IP User Guide" in which encoding is done in FPGA logic so I guess that for F-tile it has be done like this?

Regards

Mike

[Harshx]

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[Harshx]

Hi Mike,

Can you please share details about what device you are using (OPN number) in Agliex 7.

Yes, its mentioned in 12.1.2. PCS Features in E-Tile Transceivers (intel.com) that it supports 64b/67b.

You can refer: 1.8.1.2. PCS Features (intel.com)

It's mentioned that "The Enhanced PCS mode supports 64B/66B and 64B/67B encoded applications up to 58 Gbps"

Regards,

Harsh M

[mikefr]

Hello,

I have contacted my FAE about this and he told me that it is a mistake in the document, E-tile doesn't support 64b/67b in PCS.

It is like the F-tile for 64b/67b it has to be done in FPGA logic.

Unfortunately there is no example design for this.

Regards

Mike

[Harshx]

Hi,

Thank you for your information. I hope it'll be updated soon.

I'm closing the incident.

Regards,

Harsh M