Hello Intel , will appreciate answer for the below :
I am designing to Cyclon10-GX 10CXYF780E6G (780 pins) .
It’s a migration from Arria-2 DDR2 333.33Mhz and NIOS with emif_usr_clk logic running @75Mhz to DDR3 800Mhz with emif_usr_clk of 200Mhz .
I have few issues with regard to the DDR3 EMIF usage :
1. I want to clock my logic and NIOS with the DDR3 emif_usr_clk.
If i use the 800Mhz clock , How can i clock my logic and NIOS with less then quarter of 800Mhz (less of 200Mhz)- this in order to meet timing and relax paths seen in attached picture-1?
i Can use the PLL option to a lower frequencies but i understood that its not recommended as this will not be phase aligned to the emif_usr_clk - as written in the EMIF handbook...
2. Question about the C10 dev Kit: I think also of using DDR3 like on the C10 Dev kit (1866MT/s) , but the QSYS EMIF PLL don’t have option of 21.186MHz freq like on the C10 Dev kit.
selecting from the EMIF IP the C10 Dev Kit DDR gives also 933.333mHz while the Dev Kit says its 933Mhz. Neither 933.33 MHz or 933.0 MHz give option for PLL ref input of 21.186 MHz like on the Dev board - why is that ? Only if selecting 933.0 MHz there is option of 233.25 MHz like on the Dev kit but on the Dev Kit the Resistors for this option are N/A...but running 21.186MHz on the board is better then running 233.25 MHz on the board.
3. I let the fitter freely constrain DDR3 pin allocation to 2 banks of 1.5V , Please see attached picture-2. is this allocation OK ?
Or is just It better to copy the same pins like on the eval board to be on the safe side?