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EP1K50 Pin Assignment Issues


We are working with an older Altera EP1K50TC144-1 part. We are using Quartus 9.2 to create programs using Altera HDL (This is a legacy design that we needed to make some small updates to). The FPGA is at approximately 92% LE utilization.


The first issue is that we had an encoder input wired to an unused pin (Pin 118) and we found that the unused (meaning not used in design and also not "reserved" in the pin list) means that the FPGA was attempting to ground the pin, which would cause noise problems on our board because when the encoder signal came through, the ground would get bounced.


Question 1: Is it expected that unassigned pins are set output and pulled down, rather than tristated?


Then, when we set Pin 118 to "Reserved, Input Tristate" through the Pin Assignment Editor, we found that pin 33 started to be held at +0.95V (which is odd, since this is not a signal voltage for this board). Reserving or assigning Pin33 as input tristate, or output GND or output VCC has no effect on this behavior.


Question 2: Is there something that could cause the pin reservation on Pin 118 to output a +0.95V signal on another pin (Pin 33)?





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Hi Kyle,

Thanks for the question, to answer the above question I would like to set the expectation as I do not have the internal document to verify.

But in Generic Quartus environment the pin will assigned to tri state. . The above voltage as per me may be coming from another devices from the board.


We have lifted Pin33 from the board to verify that the voltage is not coming from the board - it is definitely coming from the FPGA itself.


If there are other pins we need to lift to verify, please let me know what they are - this failure is a high priority for us, and we cannot explain this behavior.