EP3C40F780C8N devices damaged after reflow

[Altera_Forum]

Hi All, 

 Has anyone had any production problems with the EP3C40 having low resistance shorts between IO pads and ground after reflow? We are getting a lot of boards failing this way.   Things that we are doing well is preparation and handling of the devices prior, the temp profile during assy (if anything we are slightly cooler) and handling of the finished board after assy.   We confirmed it wasnt the board by removing the FPGA. The FPGA still exhibits the fault, the board shows no sign of the fault once the FPGA is removed, and the board is recovered with a new FPGA installed. Although this is a solution, its getting expensive replacing all these EP3C's. We are about to produce another 4000, so we really need it solved.      any help or idea's would be much appreciated.   thanks, Steve   Request No:10757686

[Altera_Forum]

Did you x-ray the board? Or inspect the inner ball connects with an endoscope camera? I rather expect solder than device internal shorts. 

 P.S.: I didn't read the post completely. You verified internal shorts. That's rather unusual in my opinion. Did you keep the storage time after opening the dry device packing. Risk of package delamination due to adsorbed moisture is the most critical issue, I think.

[Altera_Forum]

--- Quote Start ---  Did you x-ray the board? Or inspect the inner ball connects with an endoscope camera? I rather expect solder tha device internal shorts.  --- Quote End ---     Yes, we had several xrays, and they look very clean - no shorts, very concise balls. We actually went a step further and decided to apply a small electric pulse across the shorted IO and ground to see if we could clear the fault. (anything suffering tin whiskers on lead free clears this way).   We place 4VDC, with GND to GND and 4V to the IO pin (which is reverse bias to the protection diodes) briefly across the effected pin. And it cleared the pin and recovered the board! The once dead Ep3C40 passed all its ATE tests.   If it was a PCB failure, i would expect this to be quite explainable, however, the fault definitely manifests itself in the FPGA, as removing the FPGA and replacing it also resolves the problem.   I havent used the endoscope camera as yet, but i did, very gently "rip" the FPGA from a board to inspect the balls - all is very clean, with no white lead free residue under the device - seems perfect.

[Altera_Forum]

--- Quote Start ---  The once dead Ep3C40 passed all its ATE tests.  --- Quote End ---   Very strange. You should contact Altera.

[Altera_Forum]

--- Quote Start ---  Very strange. You should contact Altera.  --- Quote End ---       I did contact Altera - the first thing I did when I was seeing the fault moving with the FPGA's. This issue is very urgent for us, as it is holding up one of our lines-    This is the ramblings I got back from Altera.   -------------------------------------------------------------------------- Hi Steve   Apologize for the delay in response as the SR was floating over and only routed to me today.   The lead-free device reflow temperature is in the 245°C to 260°C range, depending on the package size (Table 2 on page 5). From the temperature profile provided, it seem customer using lower temperature, 230°C-240°C. I recommend they check their reflow profile against our recommendations and also the handling procedure of the devices before manufacture, this includes storage and baking before reflow. Please refer to AN353 for the recommended lead free device reflow profile.   You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that. You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that. If you measure on the powered up board, and find that the IO pins is almost short to ground, it may have several possibility to have caused this:   First is the short circuit in the board trace, and second would be the EOS (electrical over stress) issue. This may be caused during reflow or just by someone touching the device or board without discharging themselves first. If the IO pin is by any chance supplied with the voltage or current larger then the absolute maximum rating mentioned in the handbook, it will cause permanent electrical damage to the IO buffer.   In order to avoid electrical damage, the device should always be handled in a static-free environment and all the input signals should remain within specified limits, as recommended in the Altera Data Book, at all times.   Thank you for contacting Altera mySupport.   Regards Ai Phing   -------------------------------------------------------------------------

[Altera_Forum]

--- Quote Start ---  You may have this low impedance value between BGA balls before powering up the device. It's quite normal for a un-powered up FPGA, so we do not measure that.  --- Quote End ---   It seems to me, that the Altera support person isn't familiar with Cyclone III technical data, particularly the hot-socketing specification. Low impedance can be possibly expected for supply pins, but not for I/O. The specification doesn't tell an input resistance, but guarantees |Iopin| < 300 uA for the unpowered FPGA and during power-up. Reading the specification strictly, the measurement current shouldn't be too small when checking for circuit shorts with an in-circuit tester.  Solder shorts and ESD induced damage are a possible explanation, generally. After you sorted out the former, EOS should be considered. I can't determine the likelihood for the specific process, you have to check it thoroughly. In my opinion, massive ESD issues in the process can be explained only by either complete ignorance to handling rules or badly designed process equipment.