Any layout guide for EP4CE15M9I7N for DDR2 routing?
As it's very small pintch 0.5mm, and we need to consider impedance match, it's not easy to route the trace. Any layout guide line?
In the pinout file, it defines T3 of Bank3 as DQS.
1） Only this pin can be used as DQS?
2) DQS pin of DDR2 ram is differential, why it specified only one pin?
Unfortunately, the layout for the EPACE15M9I7N is not available.
The PIN_T7 should be assigned as DQS pin location.
But if you find that the DQS is differential, you can let the Quartus to assign the other pin location during the Fitter compilation.
The DDR2 interface are differential or single ended.