EP4CE15U14A7N DDR2 interface

[lipingx]

Use bank 2, 3, 4 for ddr2: micron MT47H128M16RT-25E:C TR

question:

1) only 1 DQS pin marked in pin list, how to handle LDQS and UDOS?

2) The DDR2 DQS pin is differential, but FPGA is single end, how to handle?

3) For DM pin, DM5B0 is for LDM or UDM?

[AdzimZM_Intel]

Hi,

For your information, Cyclone IV devices do not support differential strobe pins.

This feature is optional in DDR2 SDRAM device.

Please my answer to your question in point below:

1) only 1 DQS pin marked in pin list, how to handle LDQS and UDOS?

• DDR2 SDRAM interfaces use x8 mode DQS group regardless of the interface width.
• For wider interface, you can use multiple x8 DQ groups to achieve the desired width requirement.

2) The DDR2 DQS pin is differential, but FPGA is single end, how to handle?

• The DDR2 SDRAM can support single-ended mode.
• You may refer to memory datasheet in page 84 to disable the DQS# ball.

3) For DM pin, DM5B0 is for LDM or UDM?

• LDM is DM for lower byte DQ [7:0] and UDM is DM for upper byte DQ[15:8]
• Use multiple x8 DQ groups to achieve the desired width requirement.

Regards,

Adzim

[lipingx]

Hi Adzim,

So it means I need to use bank 3 and bank 8 to archieve the ddr2 interface of 16 bit width, right?

Can you still other free IO for general purpose if  free bank 3 IO which is not used for DDR?

[lipingx]

talk more on it:

Then the only choice to get 16 bit done are to use bank 3 and bank 8 together, but one bank located at top side, the other bank located at bottom side. I am not sure if it's the right way. Generally they should be located nearby bank for one ddr chip.

if I assigned bank3 and bank 4 as ddr and there are still some free 1.8V IO not used, can I assign the free IO for other function?

For example: some bank3 IO are assigned to ddr, some bank3 IO are assigned to spi, general input and output.

[lipingx]

But in below document, it tells current device can support 16 bit DDR at top or bottom.

It doesn't need both. but in your pin list, the only 1 DQS pin assigned.

So your documents doesn't match, please check why.

[lipingx]

[FvM · Accepted solution]

Hi,

just read the device manual and pin list thoroughly.

Post #1 is quoting the DQS for x16/x18 column, however as clearly written in the device manual and stated in post #2, DDR2 RAM has to use x8/x9 DQS configuration. There are more DQS pins available for x8/x9, e.g. M7 and T7 in bottom banks B3/B4.

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.