Hi, we are using PCIE Express Hard IP to interface both PowerPC and Intel X86.
The difference that influences our FPGA user logic is the endianness of two processors.
PowerPC is Big endian while Intel X86 is little endian.
From IP Compiler for PCI Express User Guide, Mapping of Avalon-ST Packets to PCI Express TLPs is below:
Notes to Figure 5–17:
(1) Header0 ={pcie_hdr_byte0, pcie_hdr _byte1, pcie_hdr _byte2, pcie_hdr _byte3}
(2) Header1 = {pcie_hdr_byte4, pcie_hdr _byte5, header pcie_hdr byte6, pcie_hdr _byte7}
(3) Header2 = {pcie_hdr _byte8, pcie_hdr _byte9, pcie_hdr _byte10, pcie_hdr _byte11}
(4) Data0 = {pcie_data_byte3, pcie_data_byte2, pcie_data_byte1, pcie_data_byte0}
(5) Data1 = {pcie_data_byte7, pcie_data_byte6, pcie_data_byte5, pcie_data_byte4}
(6) Data2 = {pcie_data_byte11, pcie_data_byte10, pcie_data_byte9, pcie_data_byte8}.
It seems headers are little endian, payloads are big endian.
Is there any configuration about endianness needed to be set?
How does this IP process the endian difference?
