Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21323 Discussions

Error (10528): VHDL error at lcd.vhd(135): value "0" is outside the target constraint

Altera_Forum
Honored Contributor II
2,846 Views

I had upload a vhd file, please help me check. 

The error is at the line 135 : signal lcd_cmd_ptr : integer range 0 to LCD_CMDS'HIGH + 1 := 0; 

 

I have no any idea about it. Please help me solve it, thanks!
0 Kudos
11 Replies
Altera_Forum
Honored Contributor II
1,520 Views

you get this error while simulating or during compilation? 

Wheres the testbench?
0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

Just a quick try change X to x

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

i get this error when i doing full compilation

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

 

--- Quote Start ---  

Just a quick try change X to x 

--- Quote End ---  

 

the result still same
0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

Info: ******************************************************************* 

Info: Running Quartus II Analysis & Synthesis 

Info: Version 9.1 Build 222 10/21/2009 SJ Web Edition 

Info: Processing started: Sat Dec 01 15:14:44 2012 

Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lcd -c lcd 

Info: Found 2 design units, including 1 entities, in source file lcd.vhd 

Info: Found design unit 1: lcd-Behavioral 

Info: Found entity 1: lcd 

Info: Elaborating entity "lcd" for the top level hierarchy 

Warning (10445): VHDL Subtype or Type Declaration warning at lcd.vhd(135): subtype or type has null range 

Error (10528): VHDL error at lcd.vhd(135): value "0" is outside the target constraint range (0 to -2147483623) 

Error: Can't elaborate top-level user hierarchy 

Error: Quartus II Analysis & Synthesis was unsuccessful. 2 errors, 1 warning 

Error: Peak virtual memory: 223 megabytes 

Error: Processing ended: Sat Dec 01 15:14:45 2012 

Error: Elapsed time: 00:00:01 

Error: Total CPU time (on all processors): 00:00:01 

Error: Quartus II Full Compilation was unsuccessful. 4 errors, 1 warning
0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

I compiled it in modelsim with no error

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

i compiled it in quartus II 9.1

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

it no shows error when i click analysis current file, but it shows error when i click start compilation.

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

try giving LCD_CMDS a specified range, or change the LCD_CMDS_T to natural range instead of integer.

0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

 

--- Quote Start ---  

try giving LCD_CMDS a specified range, or change the LCD_CMDS_T to natural range instead of integer. 

--- Quote End ---  

 

thank you very much!!! it works!!!
0 Kudos
Altera_Forum
Honored Contributor II
1,520 Views

 

--- Quote Start ---  

try giving LCD_CMDS a specified range, or change the LCD_CMDS_T to natural range instead of integer. 

--- Quote End ---  

 

 

Thanks, it works!
0 Kudos
Reply