Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Altera_Forum
Honored Contributor I
1,976 Views

Error (10686) Aggregate value

Hi, 

 

I am trying to use a reduction operator on a wire to check for zero. I used to do this all the time using model sim, but now it seems there is some problem with using any reduction operator.  

 

The offending block: 

 

// control logic block always @ ( Ctrl, A, B ) begin case (Ctrl) // arithmetic operations 3'o0, 3'o1, 3'o4: begin Z = ~|Ath_out ; // high if zero <- Error!!! V = V_ath ; // set to Arith_16b overflow output N = Ath_out ; // MSB is sign bit end // logical operations 3'o2, 3'o3: begin Z = ~|Log_out ; // high if zero <- Error!!! V = 1'b0 ; // reset N = 1'b0 ; // reset end // shifts do not change flags default: begin Z = Z ; V = V ; N = N ; end endcase end 

 

The error in the analysis stage this produces is: 

Error (10686): SystemVerilog error at ALU_16b.v(99): Ath_out has an aggregate value 

Error (10686): SystemVerilog error at ALU_16b.v(105): Log_out has an aggregate value 

 

Ath_out (Log_out) is the output of a submodule defined here: 

 

// module outputs wire Ath_out ; // arithmetic output wire V_ath ; // overflow flag from arith module wire Log_out ; // logical output wire Sft_out ; // shift output 

 

and BITWIDTH is a parameter defined by: 

 

parameter BITWIDTH = 16 ; 

 

I am pretty clueless about what the problem is. I've tried not using the parameter and just hard coding the bitwidth in but the same error occurs. Any help would be greatly appreciated.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor I
556 Views

Not sure if this will fix your error, but I see one issues: 

 

Change your always block from: 

// control logic block 

always @ ( Ctrl, A, B ) begin 

... 

 

to  

 

// control logic block 

always @ ( * ) begin 

 

Your sensitivity list is incomplete, and can cause differences between synthesis and simulation..
Altera_Forum
Honored Contributor I
556 Views

 

--- Quote Start ---  

Your sensitivity list is incomplete, and can cause differences between synthesis and simulation..  

--- Quote End ---  

 

 

Oops... :oops: 

 

I'll give that a try tonight, thank you.
Altera_Forum
Honored Contributor I
556 Views

Well the problem was that i was defining my vectors as unpacked arrays 

 

wire Ath_out ; // arithmetic output 

 

needs to be: 

 

wire Ath_out ; // arithmetic output 

 

Apparently the former will compile in system verilog. Hopefully someone else learns from this. :cry:
Altera_Forum
Honored Contributor I
556 Views

 

--- Quote Start ---  

Well the problem was that i was defining my vectors as unpacked arrays 

 

wire Ath_out ; // arithmetic output 

 

needs to be: 

 

wire Ath_out ; // arithmetic output 

 

Apparently the former will compile in system verilog. Hopefully someone else learns from this. :cry: 

--- Quote End ---  

 

 

Thanks very much - this helped me a lot. I knew about the packed form, but forgot it and got this error. Thanks!
PTorr1
Beginner
556 Views

Hi there, I believe the migration of this forum page from the Altera forum to the Intel forum may have gone a bit wrong.

 

I am guessing that on the previous examples this is what the authors meant:

 

wire Ath_out [3:0] ; // un-packed array wire [3:0] Ath_out ; // packed array

If someone can confirm that would be great!

Reply