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Hello, i have an issue on this vhdl code, i need to increment the index of my vector to fill up a memory. the problem is that quartus reports me this error when i try to put a variable as an index like ( A downto B) where A and B are variables...
thank you for the help! here is the code:- LIBRARY ieee;
- use IEEE.STD_LOGIC_1164.ALL;
- use IEEE.STD_LOGIC_SIGNED.ALL;
- USE ieee.numeric_std.all;
- USE std.standard;
- entity memory is
- Port ( Clk : in std_logic; -- processing clock
- wr : in std_logic; -- write enable signal
- cs : in std_logic ;-- select memory
- rd : in std_logic; -- enable reading from memory
- add : in std_logic_vector(9 downto 0); -- write address to store the data into ram
- data_in : in signed(7 downto 0); -- input data to store into ram
- data_out : out signed(7 downto 0)); -- output data from memory
- end memory;
- architecture Behaviour of memory is
- signal tmp: integer range 0 to 1023 := 0 ;
- signal tmp1,tmp2: integer range 0 to 8184:= 0;
- signal storage: signed (8184 downto 0);
- begin
- tmp <= to_integer(unsigned(add));
- tmp1 <= 7+ tmp*8;
- tmp2 <= tmp*8;
- process(Clk)
- begin
- if Clk'event and Clk = '1' then
- if (wr = '1' and cs='1') then -- In this process writing the input data into memory
- storage(tmp1 downto tmp2) <= data_in;
- end if;
- if (cs='1' and rd='1') then
- data_out <= storage(tmp1 downto tmp2) ;
- end if;
- end if;
- end process; -- asynchronous reading from memory
- end Behaviour;
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Which line is line 30?
Could you edit your post so it is using code tags so the formatting isa bit better?- Mark as New
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edited, thanks
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Why have you got such a large signed number? if you are intending on using a ram you should use an array of signed, not a single signed, and then index to a single element on any given clock cycle.
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According to VHDL rules, you should use this straightforward coding
storage(7+ tmp*8 downto tmp*8) <= data_in;
…
data_out <= storage(7+ tmp*8 downto tmp*8);
Even more straightforward, an array 1024x8.
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