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Altera_Forum
Honored Contributor I
1,288 Views

Error (10779): VHDL error at memory.vhd(30): expression is not constant

Hello, i have an issue on this vhdl code, i need to increment the index of my vector to fill up a memory. the problem is that quartus reports me this error when i try to put a variable as an index like ( A downto B) where A and B are variables...  

thank you for the help! 

here is the code: 

 

 

 

  1. LIBRARY ieee; 

  2. use IEEE.STD_LOGIC_1164.ALL; 

  3. use IEEE.STD_LOGIC_SIGNED.ALL; 

  4. USE ieee.numeric_std.all; 

  5. USE std.standard; 

  6.  

  7. entity memory is 

  8. Port ( Clk : in std_logic; -- processing clock 

  9. wr : in std_logic; -- write enable signal 

  10. cs : in std_logic ;-- select memory 

  11. rd : in std_logic; -- enable reading from memory 

  12. add : in std_logic_vector(9 downto 0); -- write address to store the data into ram 

  13. data_in : in signed(7 downto 0); -- input data to store into ram 

  14. data_out : out signed(7 downto 0)); -- output data from memory 

  15. end memory; 

  16.  

  17. architecture Behaviour of memory is 

  18. signal tmp: integer range 0 to 1023 := 0 ; 

  19. signal tmp1,tmp2: integer range 0 to 8184:= 0; 

  20. signal storage: signed (8184 downto 0); 

  21.  

  22. begin 

  23. tmp <= to_integer(unsigned(add)); 

  24. tmp1 <= 7+ tmp*8; 

  25. tmp2 <= tmp*8; 

  26. process(Clk) 

  27. begin 

  28. if Clk'event and Clk = '1' then 

  29. if (wr = '1' and cs='1') then -- In this process writing the input data into memory 

  30. storage(tmp1 downto tmp2) <= data_in; 

  31. end if; 

  32.  

  33.  

  34.  

  35. if (cs='1' and rd='1') then 

  36. data_out <= storage(tmp1 downto tmp2) ; 

  37. end if; 

  38. end if; 

  39. end process; -- asynchronous reading from memory 

  40.  

  41.  

  42.  

  43.  

  44. end Behaviour; 

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4 Replies
Altera_Forum
Honored Contributor I
95 Views

Which line is line 30? 

Could you edit your post so it is using code tags so the formatting isa bit better?
Altera_Forum
Honored Contributor I
95 Views

edited, thanks

Altera_Forum
Honored Contributor I
95 Views

Why have you got such a large signed number? if you are intending on using a ram you should use an array of signed, not a single signed, and then index to a single element on any given clock cycle.

Altera_Forum
Honored Contributor I
95 Views

According to VHDL rules, you should use this straightforward coding 

 

storage(7+ tmp*8 downto tmp*8) <= data_in; … data_out <= storage(7+ tmp*8 downto tmp*8); 

 

 

Even more straightforward, an array 1024x8.
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