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I'm using Quartus 18.1 and Normal IEEE Libraries (my device is the MAX 10 CPLD). However, when I compile the design it declares the above error during Analysis & Synthesis process. Can anybody tell me what that is and how can I go about resolving the error so it won't repeat? Your help is urgent and appreciated. Thanks, ~Fouad Elayyach
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Seem same issue with some discussion. Please take a look.
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As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to https://supporttickets.intel.com/, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 5/5 survey

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