Error (275033) How to handle multi-bit port connections in Verilog and Quartus?

[ErenYagar]

Hello everyone!

Recently, I encountered an issue while designing FPGA circuits using Verilog and Quartus, and I would like to seek your advice. I'm trying to connect a multi-bit port, but during compilation, I'm encountering the following error:

Error (275033): Can't find name for bus

This error has left me a bit puzzled, and I'm unsure about the proper solution. I want to correctly connect these multi-bit ports to achieve the desired functionality. Could you please share any suggestions or experiences you have when dealing with similar situations?

Thank you very much for your help and suggestions!

[FvM]

Hi,
drawing lines doesn't assign a bus name. Need to assign label A explicitely to the bus.

[ShengN_Intel]

Hi,

The bus wire needs to be assigned the name as well (Right-click -> Properties) in your case is A[3..0].

You can leave them unconnected also (check image attached) because they will be connected automatically after compilation, but just make sure those wire naming are matching.

Thanks,

Best Regards,

Sheng

[sstrell]

Along with what's mentioned above by others, it looks like your schematic wires are touching the inner block of the symbol, not the I/O connection on the outer rectangle (yet another reason to use HDL instead of schematics).  You've done it correctly on the right (notice you can still see the blue I/O).

[ShengN_Intel]

Hi,

Any further concern or consideration? Does the problem being resolved?

Thanks,

Best Regards,

Sheng