Error 275062

[Altera_Forum]

Hello, 

My design is a schematic entry utilizing a top level .bdf file consisting of a symbol of a lower level .bdf. The lower level .bdf file consists of symbolized .bdf subcircuits connected with wires and also includes a few AND2 and NOT gates.   Upon Analysis & Synthesis I receive a compilation error message: "Error (275062): Logic function of type AND2 and instance "inst2" is already defined as a signal name or another logic function." Similar error messages are also listed for the other AND2 and NOT gates.   Can anyone help? I can't find any reference to this error in any Altera documentation. Does a list of error codes with brief descriptions exist? Thanks.

[Altera_Forum]

I would have thought the error was fairly self explanitory. You have two things named as "inst2".

[Altera_Forum]

No, each error message line lists the respective part label - inst2, inst3, inst4, etc. I did not repeat the part labels in the schematic.

[Altera_Forum]

have you labelled any signals as "and2"?

[Altera_Forum]

No. 

 When creating the lower level .bdf files, I kept the auto assigned inst'N' part labels for each gate and megafunction. However, no repeat labels exist within each .bdf file. The lower level .bdf files were symbolized and put into a higher level .bdf file. Consequently, an 'inst2' gate is in one lower level .bdf and a different 'inst2' gate is in another lower level .bdf file. But again, no repeat labels exist within a single .bdf file. Would this cause the aforementioned error?

[Altera_Forum]

It shouldnt clash, but then I (and most other people ) dont use schematics. 

 Any chance you can post the project?

[Altera_Forum]

It did clash. Changing all of the instance names in the project to "inst1" through "instN" cleared the compilation errors. 

 I'm old school and prefer schematic entry. The arguments in favor of an HDL-based design are uncompelling to many outside the confines of the Altera Forum.

[Altera_Forum]

Im sorry if this may be offensive, but the only people I have seen do schematic entry have been "oldschool", and refused to change. The designs that were passed to me were terrible and very difficult to debug, but this is most likely lack of documentation and the very poor way the blocks were connected back and forth across the schematics. I have also seen equally bad HDL.  

 I assure you that the market outside the altera forum is very large, and the schematic entry community is miniscule. Job prospects for schematic entry people are rather poor (for FPGA designers).

[Altera_Forum]

--- Quote Start ---  It did clash. Changing all of the instance names in the project to "inst1" through "instN" cleared the compilation errors.  I'm old school and prefer schematic entry. The arguments in favor of an HDL-based design are uncompelling to many outside the confines of the Altera Forum.  --- Quote End ---    I also use schematic entry and find they are easy to work with. There is a reason why so many software programs have graphic entry such as Cypress PSOC, Microchip, Labview, Simulink, and even Xlinx all have a graphic programming interface. I think if you are a developer that is doing a full design then using schematics is a good way to show the connectivity of your HDL modules. The big problem in using them in your design is that ModelSim doesn't accept them. So you must convert the .bdf file to HDL using File>Create/Update>Generate HDL Design File from Current File and then add that file to the project and make sure the .bdf is not in your project. With that I can use schematics and able to quickly hand off my design to other engineers and not spend time using VISO or Power Point to document the design. Everyone that I have worked with has used .bdf files. I'm told that Xilinx has a built-in Simulator that accepts the graphical files in Xilinx. Our design team have been using Quartus for so long it would be hard to make the switch to Xilinx. Last, if you are designer that is working on one portion of a design then I can understand using schematic may be a pain but I think the idea that schematics like circuit schematics help show connectivity is very beneficial.

[Altera_Forum]

--- Quote Start ---  It did clash. Changing all of the instance names in the project to "inst1" through "instN" cleared the compilation errors.  I'm old school and prefer schematic entry. The arguments in favor of an HDL-based design are uncompelling to many outside the confines of the Altera Forum.  --- Quote End ---     -bababooey  I get the same errors too and do what you did to get the errors to go away. Did you ever submit a Service Ticket and get a solution to the problem?

[Altera_Forum]

--- Quote Start ---   Our design team have been using Quartus for so long it would be hard to make the switch to Xilinx.   --- Quote End ---    I think you just pointed out a major flaw yourself. Stick with the graphical tools and you get stuck in a rut. If graphical files were: 1) Industry Standard and portable 2) Played nice with version control  They would be much more usable. But the problem is they are not, and unlikely to be so any time soon. Graphical designs are a great way tool vendors can lock you into their tools. But consider these: 1. What would you do if you wanted a new job that used xilinx? 2. What if the licence server is down today? 3. What if you have some issue that is not obvious and you want to see whats changed over the last few revisions to try and nail down the problem? 4. You wanted to port your old design to xilinx.  With graphical files, you're kind of stuck if any of the above happen. But when using just HDL - you know you can mitigate all of the above with a simple text editor that you can get for free.   Graphical design has been bashed out of me after seeing several badly written graphical projects (I have also seen well made ones, but I was usually lumbered with the bad ones) and now the need to support the same code across platform. Plus, with serious usage of SVN and multiple designers modifying the project over the years, seeing the history is very useful!