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Altera_Forum
Honored Contributor I
2,336 Views

Error:Connected system timestamp not found on target at expected base address.

Hi, 

 

I'm fairly new to FPGA programming, please bear with me.  

I tried to use Nios II and Quartus II 10.1 on Windows 7(64 bit) to programme a Altera DE2-70 board. 

 

I basically followed these procedures: 

1) Generate the SOPC which includes the Jtag Uart 

2) add all files into the quartus II project and compile 

3) Programme the board 

4) Create a project including the application and bsp  

5) Build the project 

6) Run the project as Nios II hardware 

 

Then it gives me the error:connected system id hash not found on target at expected base address 

I tried to follow the posts from the forum and ignored the mismatch in Systemid and System timestamp. Then it gives me: downloading elf process failed

If I click System ID Properties I get: 

Expected system ID base address: 0x0 (as in SOPC) 

Expected system ID:0x0 

connected system id: not found 

Expected system timestamp:1343399230 (as in SOPC) 

connected system timestamp: not found 

 

May I know what are the possible issues? 

Any suggestions would be much appreciated .
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12 Replies
Altera_Forum
Honored Contributor I
244 Views

You shouldn't ignore the mismatch in system id and timestamp. If there is a mismatch, it means there is a problem with the hardware configuration. Are you sure the project compiled correctly and that there were no errors when configuring the FPGA? Are you sure you selected the correct .sof file when programming the FPGA? If you use cores you don't have the license for, then the generated .sof file will have a _time_limited suffix, so be sure you select the right one.

Altera_Forum
Honored Contributor I
244 Views

Hi Daixiwen: 

Thank you for your reply. I am pretty sure that I have compored and configured the FPGA and used the _time_limited sof file. 

When I use the Nios2 command shell: nios2-terminal 

it shows: 

nios2-terminal:connected to hardware target using JTAG UART on cable 

nios2-terminal:"USB Blaster [USB]", device 1, instance 0 

nios2-terminal:<Use the IDE stop button or Ctrl+C to terminate> 

I guess the device is correctly connected and should be able to download the hardware program. 

But it still gives me the error about system id and timestamp mismatch. 

Is there any other possible bugs that could result in such error? 

Thank you! 

Jia Yang
Altera_Forum
Honored Contributor I
244 Views

Yes it looks like there is something in the FPGA that is working, at least. Be sure you don't close the opencores evaluation window as it will make the CPU stop and won't let you read the system ID. 

You can try and open System Console and use it to read directly the two registers from the System ID component and check what you get back. You can start withset mast 0] open_service master $mastand thenmaster_read_32 $mast 0 1should give you the ID and master_read_32 $mast 4 1should give you the timestamp. 

Are you sure the Timestamp ID component is connected to the Nios CPU's data master? Is it on a different clock domain? If yes is this clock running?
Altera_Forum
Honored Contributor I
244 Views

Hi Daixiwen: 

I tried your suggestion. It gives me some new clues which I regretfully do not know how to understand. 

First I tried to implement the instructions in the system console and here is the result 

% set mast [lindex [get_service_paths master] 0] 

/connections/USB-Blaster on localhost [USB-0]/EP2C70@1/[MFG:70 ID:34 INST:0 VER:3]/nios2_0 

 

% open_service master $mast 

 

 

% master_read_32 $mast 0 1 

error: java.lang.RuntimeException: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Can't do this while target is running 

while executing 

"master_read_32 $mast 0 1" 

 

% master_read_32 $mast 4 1 

error: java.lang.RuntimeException: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Can't do this while target is running 

while executing 

"master_read_32 $mast 4 1" 

 

But I have closed the SOPC and the programmer, I am very new and I really do not understand why it is running. 

Then I tried to look at the SOPC but I did not find the timestamp connection. 

I have attached my Printout of the SOPC file 

Thank you very much for your time and attention.
Altera_Forum
Honored Contributor I
244 Views

The Nios II processor is normally running unless it has been paused by the debugger (or by SystemConsole) 

 

You can use [processor_stop $mast] to stop the processor, and [processor_start $mast] to restart it
Altera_Forum
Honored Contributor I
244 Views

thank you for your suggestion 

I tried your command and it gives me the following error 

% [processor_stop $mast] 

error: java.lang.RuntimeException: com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset 

while executing 

"processor_stop $mast" 

invoked from within 

"[processor_stop $mast] 

I guess the problem might come from reset which is not set to high in my SOPC since the board I think is active low. But How may I set it high? Thank you.
Altera_Forum
Honored Contributor I
244 Views

the reset input on the SOPC component is active low. Check that you provide the correct polarity and that the signal is high when you try to access the processor. 

You can also try to reset the procesor with 

processor_reset $mast 

And I'm sorry for forgetting the line to stop the processor before you can read the system id.
Altera_Forum
Honored Contributor I
244 Views

I have the same problem. 

connected system id: not found 

Connected system timestamp: Not Found 

Use System Console ,it shows 

[/B][/B]com.altera.systemconsole.internal.plugin.jtag.oci.Nios2DebugException: Target is broken and needs to be reset 

while executing 

 

How can I fix it? Is the FPGA broken?
Altera_Forum
Honored Contributor I
244 Views

If I had such problems often the reason was a missed clock or active reset. Check if the clock for Nios is running and the reset is deasserted. 

Have you used the right .sopcinfo file in your Nios BSP project?
Altera_Forum
Honored Contributor I
244 Views

In your SOPC the cpu reset_n input is not connected. I've attached a screenshot of a SOPC. May be this helps you.

Altera_Forum
Honored Contributor I
244 Views

I download the same program into another FPGA board , it runs OK. Is it possible the fpga is broken?

Altera_Forum
Honored Contributor I
244 Views

 

--- Quote Start ---  

In your SOPC the cpu reset_n input is not connected. I've attached a screenshot of a SOPC. May be this helps you. 

--- Quote End ---  

 

 

I download the same program into another FPGA board , it runs OK. So I think the program is right.Is it possible the fpga is broken or other reason?
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