Error compiling my project with the standard niosII_cycloneII_2C35

[Altera_Forum]

Hi, 

i try to compile my project(DWT+NiosII_cycloneII_2c35_standard)but every time this error appear.I dont understand how to solve it: "warning: ignored 21 virtual pin logic option assignments  warning: ignored virtual pin assignment to "sdram_pll_c0_domain_reset".  warning: ignored virtual pin assignment to "pll_c1_domain".  warning: ignored virtual pin assignment to "ddr_ras_n[1]".  warning: ignored virtual pin assignment to "pll_c2_domain".  warning: ignored virtual pin assignment to "ddr_cas_n[1]".  warning: ignored virtual pin assignment to "clk_to_sdram[1]".  warning: ignored virtual pin assignment to "ddr_we_n[1]".  warning: ignored virtual pin assignment to "sdram_pll_c0_domain".  warning: ignored virtual pin assignment to "ddr_cs_n[1]".  warning: ignored virtual pin assignment to "clk_to_sdram_n[1]".  warning: ignored virtual pin assignment to "sdram_pll_c1_domain_reset".  warning: ignored virtual pin assignment to "sdram_pll_c0_out".  warning: ignored virtual pin assignment to "sdram_pll_c1_domain".  warning: ignored virtual pin assignment to "pllsysx2_c0_domain_reset".  warning: ignored virtual pin assignment to "ddr_cke[1]".  warning: ignored virtual pin assignment to "pllsysx2_c0_domain".  warning: ignored virtual pin assignment to "pll_c1_domain_reset".  warning: ignored virtual pin assignment to "pll_c0_domain_reset".  warning: ignored virtual pin assignment to "pll_c2_domain_reset".  warning: ignored virtual pin assignment to "pll_c0_domain".  warning: ignored virtual pin assignment to "sdram_pll_c1_out". error: port clk of clock delay control block "niosii_cycloneii_2c35_standard_sopc:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|dqs_delay_ctrl" must be driven by an i/o, but is currently driven by non-i/o niosii_cycloneii_2c35_standard_sopc:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:1:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]~3 error: port clk of clock delay control block "niosii_cycloneii_2c35_standard_sopc:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|dqs_delay_ctrl" must be driven by an i/o, but is currently driven by non-i/o niosii_cycloneii_2c35_standard_sopc:inst|ddr_sdram_0:the_ddr_sdram_0|ddr_sdram_0_auk_ddr_sdram:ddr_sdram_0_auk_ddr_sdram_inst|ddr_sdram_0_auk_ddr_datapath:ddr_io|ddr_sdram_0_auk_ddr_dqs_group:\g_datapath:0:g_ddr_io|altddio_bidir:dqs_io|ddio_bidir_50l:auto_generated|ddio_bidira[0]~3 info: generated suppressed messages file c:/altera/90/nios2eds/examples/verilog/niosii_cycloneii_2c35/standard/niosii_cycloneii_2c35_standard.map.smsg error: quartus ii analysis & synthesis was unsuccessful. 2 errors, 162 warnings  error: peak virtual memory: 271 megabytes  error: processing ended: sun may 02 17:36:23 2010  error: elapsed time: 00:01:46  error: total cpu time (on all processors): 00:01:44 error: quartus ii full compilation was unsuccessful. 4 errors, 162 warnings"   please if any one has an idea help me:confused::confused::confused:

[Altera_Forum]

Hi,  

 What clock have you connected to the ddr sdram in sopc builder?  Also, did you make any virtual pin assignments in the assignment editor?   Andrew

[Altera_Forum]

I connected the ddr sdram with the pll(clock clk_0) 

i didn't make anyvirtual pin in the assignement editor

[Altera_Forum]

now t have this error: 

info: ------------------------------------------------ error: post compile timing analysis failed (retcode=1) info: the most likely cause of this type of error is: info: (1) some signals on the local-side interface are not connected causing logic to be optimised away, info: this script requires that the complete logic for the specified width of the datapath (both read and write paths) be present in the design. info: (2) the clear-text hdl files for the datapath may have been modified. info: (3) not all clocks from the system pll are global. extra info: speed grade c6 used for analysis extra info: memory device can operate at 85.00 mhz with a lower cl than 2.5 info: in-system timing verification of ddr/ddr2-sdram megacore variation 'ddr_sdram_0' complete. info: please run the appropriate script for in-system verification of other ddr/ddr2-sdram megacore variations you may have in your project, and check system fmax. error: evaluation of tcl script auto_verify_ddr_timing.tcl unsuccessful error: quartus ii shell was unsuccessful. 2 errors, 0 warnings  error: peak virtual memory: 72 megabytes  error: processing ended: mon may 03 08:31:38 2010  error: elapsed time: 00:00:31  error: total cpu time (on all processors): 00:00:01 error: quartus ii full compilation was unsuccessful. 4 errors, 830 warnings

[Altera_Forum]

Can you post a readable picture of your sopc system?

[Altera_Forum]

here is my sopc:

[Altera_Forum]

The DDR SDRAM controller should be directly driven by a clock coming into the FPGA. This is because hidden in the controller is a PLL that creates all the clocks it needs. So right now, you have an input clock going to the PLL in your sopc system and then going to another PLL in the DDR controller. This is probably the source of some of your errors.  

 Also, any modules in the sopc system that are triggered by different clocks should be divided by a clock crossing bridge. Your DDR SDRAM controller is going to have to be behind one of these clock bridges, then you'll be using the sys_clk that it generates to trigger the other modules around it.   Check out the "nios architect tutorial", or the ddr controller handbook or tutorial for more in-depth info.