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Altera_Forum
Honored Contributor I
1,848 Views

Error in Quartus' Simulation Editor

I'm doing a project using Quartus Prime 18 and today I couldn't compile the waveform file (.wvf) - even though I could do it before. Tried with other Quartus projects and the results are the same, any ideas? The error code I get from the flow progress is the following: 

 

Determining the location of the ModelSim executable... Using: c:/intelfpga_lite/18.0/modelsim_ase/win32aloem/ To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off MISC -c MISC --vector_source="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/Waveform.vwf" --testbench_file="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/Waveform.vwf.vt" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 24 18:47:32 2018 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off MISC -c MISC --vector_source="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/Waveform.vwf" --testbench_file="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/Waveform.vwf.vt" Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/" MISC -c MISC Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 18.0.0 Build 614 04/24/2018 SJ Lite Edition Info: Copyright (C) 2018 Intel Corporation. All rights reserved. Info: Your use of Intel Corporation's design tools, logic functions Info: and other software and tools, and its AMPP partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Intel Program License Info: Subscription Agreement, the Intel Quartus Prime License Agreement, Info: the Intel FPGA IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Intel and sold by Intel or its authorized distributors. Please Info: refer to the applicable agreement for further details. Info: Processing started: Thu May 24 18:47:34 2018 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/" MISC -c MISC Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file MISC.vo in folder "C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4638 megabytes Info: Processing ended: Thu May 24 18:47:35 2018 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:01 Completed successfully. **** Generating the ModelSim .do script **** C:/Users/cufar/Documents/Universidad/ElectronicaV/Trabajos Practicos/MISC/simulation/qsim/MISC.do generated. Completed successfully. **** Running the ModelSim simulation **** c:/intelfpga_lite/18.0/modelsim_ase/win32aloem//vsim -c -do MISC.do Reading C:/intelFPGA_lite/18.0/modelsim_ase/tcl/vsim/pref.tcl # 10.5b # do MISC.do # ** Warning: (vlib-34) Library already exists at "work". # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:47:36 on May 24,2018 # vlog -work work MISC.vo # -- Compiling module MISC # -- Compiling module hard_block # # Top level modules: # MISC # End time: 18:47:36 on May 24,2018, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vlog 10.5b Compiler 2016.10 Oct 5 2016 # Start time: 18:47:36 on May 24,2018 # vlog -work work Waveform.vwf.vt # -- Compiling module MISC_vlg_vec_tst # # Top level modules: # MISC_vlg_vec_tst # End time: 18:47:37 on May 24,2018, Elapsed time: 0:00:01 # Errors: 0, Warnings: 0 Errors: 1, Warnings: 0 RPC(simulator): channel sock724 read error: (134) socket is not connected (line 804) ** Fatal: Kernel lost connection to front end process. ** Fatal: (SIGSEGV) Bad pointer access. Closing vsimk. ** Fatal: vsimk is exiting with code 211. Exit codes are defined in the "Error and Warning Messages" appendix of the ModelSim User's Manual.  

 

As you see there is an error of 'socket is not connected', I'm wondering what Socket this is talking about since this is a pure software simulation.
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2 Replies
Altera_Forum
Honored Contributor I
283 Views

Hi, 

 

Can you share your design file(.qpf)? 

In which all tools you have tried to simulate? 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
283 Views

Thank you for your reply. Turns out the antivirus was blocking the application that run the waveform university program to simulate signals. I could solve the problem turning it off.

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