Error: rs232_0: The input clock frequency must be known at generation time.

[FPGAOLOG]

I try to instantiate an RS232 UART Intel FPGA IP. and it gives the following error during generation:

Error: rs232_0: The input clock frequency must be known at generation time.

I tried the workarounds available in Intel resources, Both Intel IP catalog or Platform designer does not work. Platform designer has clock source instantiated and clock frequency set properly.

21.2

[RichardTanSY_Intel]

Have you try the solutions below and see if it helps to solve your error?

https://stackoverflow.com/questions/51346684/quartus-18-ip-error

[MTw]

Thanks a lot. This solution worked for me!

[RichardTanSY_Intel]

We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel support are helpful, please feel free to give Kudos. 

[FPGAOLOG]

I have tried the solution and mentioned it did not work in the original message which was replied with the solution that did not work.