Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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Errors when implementing a SPI to configuration serial flash bridge

tedh4ddv
Beginner
298 Views

Using Quartus Prime v20.1 Std, for a Cyclone 10 LP design.

The basic project compiles and functions.  The problem arises when adding an IP block to bridge an existing SPI interface to the configuration flash device interface (DATA1/ASDO, DATA0, DCLK, FLASH_nCE/nCSO). The Quartus fitter throws errors regarding I/O bank voltage incompatibility.  Apparently the configuration flash interface shares the block 1 VCCIO reference voltage which is +3.3V for this project.  The error messages imply that the flash configuration pins require +2.5V.  I tried changing the configuration pin voltage in Assignments > Device > Device and Pin Options > Configuration device I/O voltage to 3.3V with no luck.  The flash device is a 3.3V M25P128.  JTAG programming of the flash device works, so I don't understand why the IP will not compile.

 

A portion of the fitter report errors is attached.

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1 Solution
tedh4ddv
Beginner
255 Views

The issue has been resolved here.  The design now compiles.  It was the default I/O standard setting in Assignments > Device > Device and Pin Options > Voltage.  Never had to edit that in the past.  Thanks. 

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3 Replies
NurAiman_M_Intel
Employee
268 Views

Hi,


Can you provide us your design in .qar? So we can try to recompile from our end.


Thank you.


Regards,

Aiman


tedh4ddv
Beginner
256 Views

The issue has been resolved here.  The design now compiles.  It was the default I/O standard setting in Assignments > Device > Device and Pin Options > Voltage.  Never had to edit that in the past.  Thanks. 

NurAiman_M_Intel
Employee
217 Views

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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