F-tile FHT 400GE lane swap

[nujnal]

Hi！

    we are using  AGIB027R29A1E2VB FHT for 400GE-4. 

when we using （0,1,2,3）-> (0,1,2,3)   FPGA design project receive an error ：

QSFP112_RX0 ->  FHTL12A_RX_CH0

QSFP112_RX1 ->  FHTL12A_RX_CH1

QSFP112_RX2 ->  FHTL12A_RX_CH2

QSFP112_RX3 ->  FHTL12A_RX_CH3

QSFP112_TX0 ->  FHTL12A_TX_CH0

QSFP112_TX1 ->  FHTL12A_TX_CH1

QSFP112_TX2 ->  FHTL12A_TX_CH2

QSFP112_TX3 ->  FHTL12A_TX_CH3

but we using Inverse order(0,1,2,3) ->(3,2,1,0) FPGA design project works

QSFP112_RX0 ->  FHTL12A_RX_CH3

QSFP112_RX1 ->  FHTL12A_RX_CH2

QSFP112_RX2 ->  FHTL12A_RX_CH1

QSFP112_RX3 ->  FHTL12A_RX_CH0

QSFP112_TX0 ->  FHTL12A_TX_CH3

QSFP112_TX1 ->  FHTL12A_TX_CH2

QSFP112_TX2 ->  FHTL12A_TX_CH1

QSFP112_TX3 ->  FHTL12A_TX_CH0

after i check 400GE-4 example. i found example project using Inverse order(0,1,2,3) ->(3,2,1,0).

is that correct?

thanks !

[ZiYing_Intel]

Hi,

The order of channel naming is reversed order of streams in Ethernet HIP block. For further information, you can refer to link below, section F-tile Architecture, https://www.intel.com/content/www/us/en/docs/programmable/683872/24-1-4-8-0/f-tile-architecture.html

Best regards,

zying

[ZiYing_Intel]

Hi,

Since no hear any feedback from you, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread.

Best regards,

zying