1. The AGFB027R24C2E2VR0 datasheet requires LVDS reference clock input . see pic from the
datasheet Table 66 , but the Evaluation board DK-DEV-AGF027F1ES schematics ,shows its
LVPEVL Input on the notes .
the clk driver Si53254A-D02AM on the Evaluation board drives HCSL .
What should it be ? Should we drive the FGT XCVRS with LVDS or LVPECL ?
(Maybe this topic was answered in one of the threads but i feel needs to be cleared again.)
2. Are you using at this EVAL Board , external or internal termination on the AC Coupling
The dev kit uses the pins that you show in the screenshot for CXL interface (which is based on PCIe) and uses the HCSL IO standard which is nearer to the LVPECL interface.
However, if you use this F-tile for some other interface, recommend you to follow the datasheet and assign LVDS.
The decision should be based on the data rate, interface recommendation and power consumption. There are many references on internet to each of the type of interface.
We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.