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Valued Contributor III
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FIFO to SGDMA, FIFO Stays FULL memory not written.

Hello all, still a little new to NIOS and avalon components, but I've been going at it for a few days and I'm a bit stumped. 

 

I setup an external counter being fed through a custom Avalon component. This is then fed into a FIFO I setup in qsys. This works OKAY and it fills up the FIFO just fine. This is a non-packet FIFO so it's then fed into a bytes_to_packet converter (many little timing adapters and data format adapters are added auto-magically by qsys as well). This eventually makes its way to a SGDMA which is linked to onboard memory so that I can view it through the in system memory viewer.  

 

So my problem is as follows, I can feed the data into the FIFO and I signal tap the output of the FIFO and can see the data coming out for a very short time. The FIFO becomes exerts a high FULL signal and all transmission stops. I'm not sure why the DMA isn't reading data off the FIFO (or if it needs something else to do that) to keep it empty and more importantly, even though it reads a small amount of data NONE of it makes it to that onboard memory block that I can see (after firing up NIOS and setting up my descriptors as per the SGDMA example design). I attached my QSYS build and was hoping for some insight, thanks. 

 

i.imgur.com/4Yw7D.png 

 

 

Upon looking at this further, my ready_in isn't being asserted at the DMA. I'm setting the registers correctly, I've got two descriptors with the control byte of the last one set to 0 so that it's not owned by hardware. I'm guessing the DMA SHOULD be starting because I run 

 

alt_avalon_sgdma_do_async_transfer(DEVICE, &dma_descriptors) 

 

Inside the function it points the controller to the descriptor and then sets the run bit in the control register via: 

 

control = IORD_ALTERA_AVALON_SGDMA_CONTROL(dev->base); control |= (dev->chain_control | ALTERA_AVALON_SGDMA_CONTROL_RUN_MSK | ALTERA_AVALON_SGDMA_CONTROL_STOP_DMA_ER_MSK ); IOWR_ALTERA_AVALON_SGDMA_CONTROL(dev->base, control);
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Valued Contributor III
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Re: FIFO to SGDMA, FIFO Stays FULL memory not written.

I switched the design over to the modular SGDMA and use the following code to try and set things up, nothing returns any errors and all the steps seem to complete successfully but my interrupt is never fired and nothing is written to the onchip memory that I'm viewing via in system memory content editor. I can see the data coming out and it should be getting to the mSGDMA fine.... the code is below: 

 

 

int main() { int i = 0; sgdma_standard_descriptor a_descriptor; sgdma_standard_descriptor * a_descriptor_ptr = &a_descriptor; // using this instead of 'a_descriptor' throughout the code int valid = alt_ic_isr_register (NULL, MODULAR_SGDMA_DISPATCHER_CSR_IRQ, sgdma_complete_isr, NULL, NULL); // register the ISR enable_global_interrupt_mask(MODULAR_SGDMA_DISPATCHER_CSR_BASE); // turn on the global interrupt mask in the SGDMA construct_standard_st_to_mm_descriptor(a_descriptor_ptr, (alt_u32 *) ONCHIP_MEMORY2_0_BASE, 0x3fc, DESCRIPTOR_CONTROL_TRANSFER_COMPLETE_IRQ_MASK); int freq = 0; while (1) { if (sgdma_interrupt_fired == 1) { for (i = 0; i < 0x3fc; i++) { printf("%x\n", IORD_32DIRECT(ON_CHIP_MEM_BASE, i)); } sgdma_interrupt_fired = 0; } freq ++; if(freq % 10000000 == 0){ printf("Frequency set to %d.\n\r", (int) freq); if (write_standard_descriptor(MODULAR_SGDMA_DISPATCHER_CSR_BASE, MODULAR_SGDMA_DISPATCHER_DESCRIPTOR_SLAVE_BASE, a_descriptor_ptr) != 0) { printf("Failed to write descriptor to the descriptor SGDMA port."); } } } } 

 

With the qsys setup that's attached.  

 

This SHOULD work I take it and I'm at a loss as to why this wouldn't be working. I left the TSE things in qsys because that's part of the next step for me, but if any of you guys had any ideas that would be great.  

 

https://www.alteraforum.com/forum/attachment.php?attachmentid=6570  

 

 

Edit: I've since fully disabled the response port and made sure I was in 128 bit descriptor mode
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Valued Contributor III
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Re: FIFO to SGDMA, FIFO Stays FULL memory not written.

I think you forgot to start the modular SGDMA, so there is probably a descriptor stuck in the fifo waiting for the DMA to start.

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Valued Contributor III
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Re: FIFO to SGDMA, FIFO Stays FULL memory not written.

 

--- Quote Start ---  

I think you forgot to start the modular SGDMA, so there is probably a descriptor stuck in the fifo waiting for the DMA to start. 

--- Quote End ---  

 

 

How do you explicitly start the SGDMA? 

 

The following  

read_csr_control(MODULAR_SGDMA_DISPATCHER_CSR_BASE); 

 

returns 16 which from your manual should imply: Stop Descriptors is set. I try and call start_descriptors and start_dispatcher manually via 

 

start_descriptors(MODULAR_SGDMA_DISPATCHER_CSR_BASE); 

 

And if I check the control register status it's still at 16. So something isn't starting like you assumed, I'm just not sure how to get it going.
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Valued Contributor III
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Re: FIFO to SGDMA, FIFO Stays FULL memory not written.

Partially solved, the write_master wasn't hooked up to the CSR on the dispatcher, I now see the memory changing. The only problem remaining is that it still does not want to fire the interrupt 

 

Edit: Now also solved solved forgot to enable IRQ
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