FIR Compiler and FIR feedback filter.

[Altera_Forum]

Hello guys, 

 Today I'm trying implementing a FIR feedback in my design with the FIR compiler megafunction.  I've created 25 8-bit coefficients and imported them in the FIR compiler tool.  The coefficient as something similar to these ones (but mine are always positive):  http://www.mathworks.com/help/releases/R2013b/signal/ref/prony_ex1.png    Due to the feedback implementation I need that the output of the filter at time 'k' act on the input at k+1. So I need one period delay bettwen input and output.  http://www.originlab.com/www/helponline/origin/en/images/Algorithm_(IIR_Filters)/IIR_Filter_1.png  In FIR-Compiler I choose the 'fully parallel structure' option as it is supposed processing every input every clock period and generating a new output every clock period.  After I have also created the simulation files needed to simulate the filter with modelsim. Simulating the filter shows that there are about 14 clocks period delays between input samples and output samples..  I'm a little confused... Do you have any suggestions ??  Thank you very much. have a nice day.

[Altera_Forum]

you will get delay inside filter(group delay) on top of usual latency as signal builds up. 

group delay = 1/2 of filter order (if fir is symmetric)

[Altera_Forum]

--- Quote Start ---  you will get delay inside filter(group delay) on top of usual latency as signal builds up. group delay = 1/2 of filter order  --- Quote End ---    Thank you kaz !  Probably i was not clear enaugh. My filter is 1-causal. So I don't have to wait the signal to reach the maximum at (n-1)/2. I have only the causal part (eg: only the right half of a gaussian).  The impulse response is like [0 10 9 8 7 6 5 4 3 2 1 0]  So if my input at k-1 is 10 I expect to have 10 at time k at the output of the filter. But this does not happen and I can't understand why..

[Altera_Forum]

It will help if you tell us how do you measure your delay.

[Altera_Forum]

x = [10 0 0 0 0 0 0 0 0 0 0]; 

h = [0 10 9 8 7 6 5 4 3 2 1 0]; y = filter(h,1,x);  y = 0 100 90 80 70 60 50 40 30 20 10  I hope this helps

[Altera_Forum]

Thank you kaz 

 It is what I was supposed to get running modelsim.. I will take a screenshot as soon as I can

[Altera_Forum]

--- Quote Start ---  It will help if you tell us how do you measure your delay.  --- Quote End ---    So, this is the filter structure: https://www.alteraforum.com/forum/attachment.php?attachmentid=8514   And this is the modelsim output: https://www.alteraforum.com/forum/attachment.php?attachmentid=8515   The first signal is the input signal, then there is the output and finally the clock. As you see there is a delay between input and output greater than one. I can't really understand why..

[Altera_Forum]

you mean delay from first nonzero input to 1st nonzero output is so many cycles. This must be clock latency through your filter. check your pipeline settings if any. 

 additionally you need to check your scaling effect on output

[Altera_Forum]

--- Quote Start ---  you mean delay from first nonzero input to 1st nonzero output is so many cycles. This must be clock latency through your filter. check your pipeline settings if any.  --- Quote End ---    I have a pipelineLevel equals to 1. I've tried to put it to 0. Effectively the delay decreases but remains higher than one period (about ten period).. So it is not possible to use the ouput on the input at the right time...  I can try with the full symmetric structure but as I enter the filter at 75 MHz and my maximum clock rate is 150 MHz I'cant comply with the delays needed by the filter to process the input and the output (16 clocks for 1 input and 1 output).

[Altera_Forum]

try value of 10 only followed by zeros as above example then check how many zeros you get at output before 100 comes out. This way you rule out any scaling effect causing zeros at output. normally filters need registers at each mult and adders but for slow speeds one register might be enough

[Altera_Forum]

--- Quote Start ---  try value of 10 only followed by zeros as above example then check how many zeros you get at output before 100 comes out. This way you rule out any scaling effect causing zeros at output. normally filters need registers at each mult and adders but for slow speeds one register might be enough  --- Quote End ---    So this is my output with only a 10 valued input: https://www.alteraforum.com/forum/attachment.php?attachmentid=8516   It seems it leads to the same problem..

[Altera_Forum]

so it is clock latency(pipe). the fir compiler may tell you the latency through your design. 

you can readily code by hand without any registers if speed allows.

[Altera_Forum]

I don't believe that FIR compiler is designed for applications like yours (with minimal delay). But you didn't tell the implementation details so we can't check the results.  

 It isn't however too complicated to write a minimal delay FIR implementation from the scratch. 1 multiplier and 1 adder makes the shortest signal path, how many pipeline levels you place is up to you, respectively the speed requirements.

[Altera_Forum]

Thank you guys, 

 What do you mean by "implementation details" ? I have a 25 FIR taps. I have simulated the whole system with another software using the classic serial structure: http://upload.wikimedia.org/wikipedia/commons/9/95/Fir_filter_df1.png   By the way in an FPGA this structure will introduce a something like 16 delays before I can get the output (clock through whole dffs). Because I'm going at 75 MHz and I have a system clock of 150 i can speed up the system at a maximum value of 2 which is not enough.  So I have seen that the parallel structure process 1 input and 1 output in 1 clock period (so FIR compiler told me..) by the way it was not specified that there was latency to take into account. I need a FIR with 25 taps that have a 1 clock latency and 1 clock output processing..  It seems I am in a "cul-de-sac"..

[Altera_Forum]

try set FIR to transposed structure. you may then get less delay as delay stages could be used as pipeline registers between adders. 

delay in parallel structure is caused by the addition ladder

[Altera_Forum]

--- Quote Start ---  What do you mean by "implementation details" ?  --- Quote End ---   Simply all setting in the FIR compiler. But as already mentioned, the FIR compiler is probably not prepared to generate a minimal delay structure.   --- Quote Start ---  try set FIR to transposed structure.  --- Quote End ---   Yes, that's what I mean. In the transposed structure, the adder pipeline delay makes the FIR delay line.

[Altera_Forum]

Thank you guys.. I'm very busy these days.. 

 The FIR compiler can be implemented as: - Fully serial Filter -> 1 input every 16 clocks and 1 output every 16 clocks -> Not suitable. - Multi bit Serial Filter -> 1 input every 8 clocks and 1 output every 8 clocks -> Not suitable. - Fully parallel Filter -> 1 input every 1 clock, 1 output every 1 clock -> Ok but registers delay makes it not suitable - Multy-Cycle -> 1 input every 2 clocks periods and 1 output every 2 clocks period -> It would be ok because I can speedup by a 2 factor. By the way the pipeline makes it not suitable too..  I could put it down by hand but the filter taps could be much more and it would be sooooo tedious.....   I will try with few coefficients for now.

[Altera_Forum]

I have the impression that you are designing IIR filter using two FIRs(forward and feedback). Sounds good idea if it tolerates the delay. You might well see your math model if it tolerates delay and how far.

[Altera_Forum]

The transposed stucture model seems to work fine. 

 Thank you guys ! I really appreciate.