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Novice
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FIR II core IP outputs incorrect data.

Hello,

It's my first time using intel's FIR filter IP and I'm having difficulties getting it working.

I basically want to low-pass filter the data coming from the ADC (LTC2387) using FIR II IP. The filter is fractional rate filter.

Here are some of the filter specs:

Input sampling rate: 15 MSPS

Filter clock : 60 MHz

Coeffs: 51 taps, 16-bit signed binary

Input 16-bit singed binary

Output: 36-bit signed binary.

The data coming from the ADC is in 2's complement, and therefore firstly I convert it to signed binary(bit magnitude) and feed the converted data to the filter's input.

To make sure that everything's working I make the input to the filter constant and observe the output, expecting that the output stays constant as well, but it doesn't.

The input is constant -256 (FF00h in 2s complement 8100h in signed magnitude) and the output looks quite random as you can see in the attachment.

I also attached the archieve file which include the filter I am using. The filter is in pre_process_20MSPS.vhd file along with the conversion from 2's comlement to singed magnitude process.

What am I doing wrong?

 

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Novice
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The output rate is 20MSPS. I forgot to add this.

I hope someone can help me with this.

Thanks.

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Hi,


Sorry for the delay. As I understand it, you observe some issue with the FIR II IP. If I understand it correctly, you are observing it in simulation. To ensure we are on the same page, would you mind to share with me a simple Modelsim simulation example together with steps which could replicate your observation? Some screenshots to further elaborate on the issue would be very helpful. Thank you very much.


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Novice
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Hello,

Thank you for your answer,

I am observing the output of the FIR filter (FIR filter output (36 bit data)) in signal tap, so it's not modelsim simulation, it's real hardware implementation. Signal Tap file is also included in the .qar file that I shared.

I understand that the file I shared is kind of complicated it's a portion of our design we working on I am sorry for its messiness. I kindly ask you to inspect pre_process IP. I t includes the FIR filter and data conversion(2's complement to bit magnitude conversion for the input).

This is my understanding on how the IP works:

I only need a signle channel therefore the error signals kind of irrelevant (no SOP or EOP), therefore I ignored them left them 'open' in the VHDL file. Sink side has an error input I don't know what to do with that. The input is 16-bit signed binary,  I assume this bit magnitude form where the first bit is the sign and the rest is the number. The input 15MSPS, the output 20MSPS, the clock to the filter is 60MHz. What I do is I fixed the input signal at 0x8100 and assert sink valid at every 4th(60MHz/15MSPS = 4) cycle of the clock and expect the source valid to be asserted at every third cycle of the clock which is what we see in the waveform that I attached, but the output looks completely random.

What am I doing wrong? 

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Hi,


Thanks for your update. As I understand it, you are observing this in signaltap. To help isolating any functional issue, it is recommended for you to create simple test design and run through Modelsim simulation to check on the behavior. Generally the Modelsim simulation behavior is similar to the hardware behavior for this IP. This would help to isolate any functional issue prior to hardware debugging. Please feel free to keep me posted on the simulation result.


Regarding the ast_sink_error, this is to indicate AVST violation to the IP. In normal cases, you can drive the ports with 2'b00.


Regarding the SOP/EOP, yes, you are right. For single channel, you do not need these ports. By default, when you select single channel, there will be no SOP/EOP ports.


Please let me know if there is any concern. Thank you.


Best regards,

Chee Pin



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Novice
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Thank you for your kind response,

OK I am going to start with a testbench, but I want to quickly confirm one thing. Is Singed binary same as bit magnitude where the first represents the sign and the rest is the number. I am talking about Input and output type in Input/Output Options settings.

I wrote a simple test bench and tested the FIR filter (attached). I share the results with a screenshot. As you see the input is fixed at some value, the clock to the filter is 60 MHz and every fourth cycle of the I asserted the sink_valid signal for one cycle and I see don't see any output. No action from the filter.

See the attached files for the test bench it's named FIR_tb.vhd. I know there is another tb file generated by quartus, but failed to get it working. I simply instantianted pre_process_FIR_20MSPS_0002 IP and tried to get it working.

FIR_tb.vhd

Thanks in advance.

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Hi,


Thanks for your update. yes, the signed binary, the MSBits = sign bit. Please allow me some time to look into your shared test bench. I will be out of office and back on next Tuesday due to local Public holiday. I will keep you posted on the progress by mid of next week or as soon as there is any valid finding. Please ping me if you do not hear back from me.


Thank you.


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Hi,

Sorry for the delay. As I understand it from your screenshot, seems like the source data = undefined in your simulation. Sorry as I am not very familiar with VHDL and could not really further edit your test bench for testing.

To facilitate your debugging, I have generated a simple simulation example from the IP with 16 bits coeff and 16 bits input signed data using A10 in Q17.0Std. There seems to be no FIR .qsys file in your .rar, and thus I am using some dummy setting in my example. You may refer to the fir0.qsys in the test.zip. I have edited the test bench to feed constant data. From the Modelsim simulation, seems like I am able to get valid output from the IP as shown in the screenshot.

I have attached the ZIP of the simulation folder. You can run the simulation by doing the following:

1. Change directory in Modelsim to \test\fir0_tb\fir0_tb\sim\mentor\
2. Type "source msim_setup.tcl"
3. Type "ld" to compile
4. Type "do wave.do" to populate the waveform
5. Type "run -all" to run the simulation

You may further customize from this example with your input data as well as target configuration.

Please let me know if there is any concern. Thank you.


Best regards,
Chee Pin

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Novice
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Hello again

Thanks for your respose. I am going to look into it, but there is something that's confusing me about the results. The output is 7.5MSPS instead of 15 MSPS. Isn't it wrong. What am I missing here?

The reasons there is no qsys file is that I use the IP catalog directly. Should I use plaform designed instead?

Thanks.

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Novice
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Sink valid signal is also high during the whole simulation. I assumed I assert the valid signal every time I got a data which is at 15 MSPS, in this simulation it seems like you're feeding 60MSPS by asserting the sink valid signal for every clock cycle. What am I missing?

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Hi,


Your understanding is correct. In my example simulation, the valid signal is high all the time. This example is to show working simulation and for reference only. It is not matching your test bench directly.


I am using Q17.0Std to create the example. I believe you are using QPro edition. If yes, you can use the IP Parameter Editor Pro to generate the Testbench System for your FIR II IP, and then customize from there. You may refer to my example on some of the changes required to the test bench to enable simulation.


Please let me know if there is any concern. Thank you.



Best regards,

Chee Pin



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Novice
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Hello,

I am using quartus prime lite 19.1 edition.

I am able to reproduce the results that you shared, but I am just more confused (sorry for this I am kind of new to using quartus).

My first question is the rate of the output I am seeing the output data at 7.5MSPS which matches your results. THe IP is configured to be 15 MSPS. Isn't it wrong? SHouldn't we get 15 MSPS output rate?

Secondly, I don't understand how to represent the output data. The output data is 38 bits and I want to know how to make use of it? I expect the output to be 8100h after it settles, but the output data makes no sense to me. How do I represent the data?

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Hi,

Sorry if there is any confusion. Let's move to the basic mode of the FIR to ease the discussion. Then you can further customize from there.

I have create a test design with Clock Rate = Sample Rate. Then, input a pulse to the FIR IP. From the simulation, you can see the FIR output each of the coefficient in sequence which is an expected behavior. Attached is the test.zip with simulation files for your reference. You can try out on your side to verify the FIR behavior. Then, you can try with your own data.

Note that I am not sure about what should be the expected output with your input 0x8100. But after verifying the FIR is working fine with pulse, the output of the simulation should be correct. In my Modelsim simulation, I am setting the radix of my source_data = sfixed.

Please let me know if there is any concern. Thank you.

 

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