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FPGA 2 SDRAM bridge reference

Altera_Forum
Honored Contributor II
2,343 Views

hi All, 

 

I am working on design a system that FPGA can access SDRAM of HPS through F2S bridge.  

 

Where can find the reference design (include hardware / software project ) ? 

 

 

 

Thanks
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8 Replies
Altera_Forum
Honored Contributor II
135 Views

In http://www.altera.com/products/devkits/altera/kit-cyclone-v-soc.html see "Table 2. Altera´s Cyclone V SoC Development Kit Documentation", "Kit installation (EXE) (Windows)".

Altera_Forum
Honored Contributor II
135 Views

I think this thread can help you: http://www.alteraforum.com/forum/showthread.php?t=45290 I just went through it and it's explained, 

cheers
Altera_Forum
Honored Contributor II
135 Views

hi aprado,  

 

I have done the Qsys intregration as thread mentioned. but when I control the DMA to read data from HPS SDRAM into On-chip RAM of FPGA , the DMA action has finished, but the data is not consistent.  

 

Can you take a look at my Qsys design and DS-5 Bare-metal software code ?  

1) Bare-metal: https://www.dropbox.com/s/q44vgldbxc39qnj/altera-socfpga-hardwarelib-fpga-cv-gnu.7z 

2) QSYS: https://www.dropbox.com/s/z512he9nb0ma4jp/soc_system.qsys 

 

Thanks. 

 

Lucian
Altera_Forum
Honored Contributor II
135 Views

hi aprado,  

 

Can you share your Qsys file to me ?  

lucian.working@gmail.com  

 

Thanks
Altera_Forum
Honored Contributor II
135 Views

Lucian, unforunately I am not the one responsible for the software, I only made the QSys connections. I can share it with you, gonna mail you later.

Altera_Forum
Honored Contributor II
135 Views

hi aprado,  

 

Thank you very much.
Altera_Forum
Honored Contributor II
135 Views

After remove the "Address Span Extender" between DMA & Memory, the result is ok.  

 

I don't know why "Address Span Extender" will block DMA's transmission ?
Altera_Forum
Honored Contributor II
135 Views

Hi 

 

can you send me your project
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