FPGA Crypto Service -- not working

[LowLevelGuy]

What is involved in supporting the FPGA Crypto Service (FCS) on Stratix FPGAs? 

Under the Intel 6.1.55 kernel, every 10 seconds, there is a kernel message  "svc_normal_to_secure_thread: STATUS_ERROR" which is coming from the "COMMAND_FCS_RANDOM_NUMBER_GEN" mailbox command.

Following the RocketBoards guides, I am building and loading the  "bl31.bin"  arm-trusted-firmware image from u-boot SPL.   Is another component from arm-trusted-firmware also required?

[Farabi]

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[Farabi]

Hello,

The recurring message svc_normal_to_secure_thread: STATUS_ERROR suggests a failure in secure-world communication between the ARM Trusted Firmware (ATF) and the hardware. 

The bl31.bin may not include the necessary support for Secure Mailbox services, which are essential for commands like COMMAND_FCS_RANDOM_NUMBER_GEN.

Check if your ATF configuration (plat/arm/board/stratix10/) includes secure mailbox support and the appropriate platform-specific definitions. 

regards,

Farabi

[LowLevelGuy]

It seems like it does.   I am using the QPDS24.2_REL_GSRD_PR release, which seems to unconditionally compile  plat/intel/soc/common/sip/socfpga_sip_fcs.c   and plat/intel/soc/common/socfpga_sip_svc.c.  Otherwise there seems to be extremely few compile-time options (I only see USE_COHERENT_MEM and USE_COHERENT_MEM_BAR).

[LowLevelGuy]

Are there any options in the gsrd FPGA project that need to be enabled?