FPGA IO sampling rate

[Altera_Forum]

Hello experts, 

 What is the sampling rate of an FPGA when it comes to reading an IO? I have the 144C8N and would like to know what spec I am looking for to find the sampling speed for an IO.  Any tips/help is greatly appreciated.   thx,

[Altera_Forum]

it depends on the family and IO standard. provide some more insight into what you're trying to do

[Altera_Forum]

Run your timing after entering io timing constraints and you will get the result within your system. Normally the bottleneck is inside FPGAs. 

Differenetail io can be very very fast.

[Altera_Forum]

Thanks for the replies, 

 my question is more general how fast does an FPGA of that familly samples(read) the logic state of an IO.   thx,

[Altera_Forum]

Hmm... doesn't work like that. 

The input signal is continuously fed into the logic, no sampling involved.  If the logic is a FF, it will sample the signal at the edge of the clock that drives the FF. The clock is whatever signal you use as clock.

[Altera_Forum]

You will need to think separately about io toggle rate and io speed(sampling). 

 Toggle rate depends on many factors and is usually way too fast and may be available in data sheet.  here is an excerpt from altera doc: "I/O toggle rates vary based on speed grade, loading, and I/O bank location—top/bottom versus left/right. This toggle rate is also a function of the termination used (OCT or external termination) and other settings such as drive strength and slew rate."  io speed is meant to be sampling speed at io register(one clock edge sampling or both using two registers). This is what we should mean by "read" or "write". Fmax at io register depends on device and design constraints mostly and only the timing tool can best tell.  Toggle rate may at times restrict fmax and then timing report will tell under "restricted fmax", however I can guess that the tool can't detect issues like loading and external termination and hence a bad design may violate toggle rate without report from tool.