Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21153 Discussions

FPGA JTAG Circuit for Cyclone II

alparodi
Beginner
1,612 Views

Hi. I am developing a Cyclone II - EP2C20AF256I8N FPGA schematic using the EPCS16SI8N memory. I wanted to know if the following schematic is correct to program it through USB BLASTER ALTERA CPLD. If I have any mistake, could you please correct me?
Is it necessary to put the two headers to record it also by AS?Sch_JTAG.png

0 Kudos
1 Solution
FvM
Honored Contributor I
1,586 Views
Hello,
the configuration interface is implemented correctly. You don't need a second AS header, flash will be programmed through JTAG by using JTAG indirect configuration.

View solution in original post

2 Replies
FvM
Honored Contributor I
1,587 Views
Hello,
the configuration interface is implemented correctly. You don't need a second AS header, flash will be programmed through JTAG by using JTAG indirect configuration.
NurAiman_M_Intel
Employee
1,528 Views

Thank you FvM for sharing the solution.


I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


Reply